1/* 2 * Octeon Watchdog driver 3 * 4 * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks 5 * 6 * Some parts derived from wdt.c 7 * 8 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, 9 * All Rights Reserved. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 * 16 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide 17 * warranty for any of this software. This material is provided 18 * "AS-IS" and at no charge. 19 * 20 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> 21 * 22 * This file is subject to the terms and conditions of the GNU General Public 23 * License. See the file "COPYING" in the main directory of this archive 24 * for more details. 25 * 26 * 27 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. 28 * For most systems this is less than 10 seconds, so to allow for 29 * software to request longer watchdog heartbeats, we maintain software 30 * counters to count multiples of the base rate. If the system locks 31 * up in such a manner that we can not run the software counters, the 32 * only result is a watchdog reset sooner than was requested. But 33 * that is OK, because in this case userspace would likely not be able 34 * to do anything anyhow. 35 * 36 * The hardware watchdog interval we call the period. The OCTEON 37 * watchdog goes through several stages, after the first period an 38 * irq is asserted, then if it is not reset, after the next period NMI 39 * is asserted, then after an additional period a chip wide soft reset. 40 * So for the software counters, we reset watchdog after each period 41 * and decrement the counter. But for the last two periods we need to 42 * let the watchdog progress to the NMI stage so we disable the irq 43 * and let it proceed. Once in the NMI, we print the register state 44 * to the serial port and then wait for the reset. 45 * 46 * A watchdog is maintained for each CPU in the system, that way if 47 * one CPU suffers a lockup, we also get a register dump and reset. 48 * The userspace ping resets the watchdog on all CPUs. 49 * 50 * Before userspace opens the watchdog device, we still run the 51 * watchdogs to catch any lockups that may be kernel related. 52 * 53 */ 54 55#include <linux/miscdevice.h> 56#include <linux/interrupt.h> 57#include <linux/watchdog.h> 58#include <linux/cpumask.h> 59#include <linux/bitops.h> 60#include <linux/kernel.h> 61#include <linux/module.h> 62#include <linux/string.h> 63#include <linux/delay.h> 64#include <linux/cpu.h> 65#include <linux/smp.h> 66#include <linux/fs.h> 67#include <linux/irq.h> 68 69#include <asm/mipsregs.h> 70#include <asm/uasm.h> 71 72#include <asm/octeon/octeon.h> 73 74/* The count needed to achieve timeout_sec. */ 75static unsigned int timeout_cnt; 76 77/* The maximum period supported. */ 78static unsigned int max_timeout_sec; 79 80/* The current period. */ 81static unsigned int timeout_sec; 82 83/* Set to non-zero when userspace countdown mode active */ 84static int do_coundown; 85static unsigned int countdown_reset; 86static unsigned int per_cpu_countdown[NR_CPUS]; 87 88static cpumask_t irq_enabled_cpus; 89 90#define WD_TIMO 60 /* Default heartbeat = 60 seconds */ 91 92static int heartbeat = WD_TIMO; 93module_param(heartbeat, int, S_IRUGO); 94MODULE_PARM_DESC(heartbeat, 95 "Watchdog heartbeat in seconds. (0 < heartbeat, default=" 96 __MODULE_STRING(WD_TIMO) ")"); 97 98static int nowayout = WATCHDOG_NOWAYOUT; 99module_param(nowayout, int, S_IRUGO); 100MODULE_PARM_DESC(nowayout, 101 "Watchdog cannot be stopped once started (default=" 102 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 103 104static unsigned long octeon_wdt_is_open; 105static char expect_close; 106 107static u32 __initdata nmi_stage1_insns[64]; 108/* We need one branch and therefore one relocation per target label. */ 109static struct uasm_label __initdata labels[5]; 110static struct uasm_reloc __initdata relocs[5]; 111 112enum lable_id { 113 label_enter_bootloader = 1 114}; 115 116/* Some CP0 registers */ 117#define K0 26 118#define C0_CVMMEMCTL 11, 7 119#define C0_STATUS 12, 0 120#define C0_EBASE 15, 1 121#define C0_DESAVE 31, 0 122 123void octeon_wdt_nmi_stage2(void); 124 125static void __init octeon_wdt_build_stage1(void) 126{ 127 int i; 128 int len; 129 u32 *p = nmi_stage1_insns; 130#ifdef CONFIG_HOTPLUG_CPU 131 struct uasm_label *l = labels; 132 struct uasm_reloc *r = relocs; 133#endif 134 135 /* 136 * For the next few instructions running the debugger may 137 * cause corruption of k0 in the saved registers. Since we're 138 * about to crash, nobody probably cares. 139 * 140 * Save K0 into the debug scratch register 141 */ 142 uasm_i_dmtc0(&p, K0, C0_DESAVE); 143 144 uasm_i_mfc0(&p, K0, C0_STATUS); 145#ifdef CONFIG_HOTPLUG_CPU 146 uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), label_enter_bootloader); 147#endif 148 /* Force 64-bit addressing enabled */ 149 uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX); 150 uasm_i_mtc0(&p, K0, C0_STATUS); 151 152#ifdef CONFIG_HOTPLUG_CPU 153 uasm_i_mfc0(&p, K0, C0_EBASE); 154 /* Coreid number in K0 */ 155 uasm_i_andi(&p, K0, K0, 0xf); 156 /* 8 * coreid in bits 16-31 */ 157 uasm_i_dsll_safe(&p, K0, K0, 3 + 16); 158 uasm_i_ori(&p, K0, K0, 0x8001); 159 uasm_i_dsll_safe(&p, K0, K0, 16); 160 uasm_i_ori(&p, K0, K0, 0x0700); 161 uasm_i_drotr_safe(&p, K0, K0, 32); 162 /* 163 * Should result in: 0x8001,0700,0000,8*coreid which is 164 * CVMX_CIU_WDOGX(coreid) - 0x0500 165 * 166 * Now ld K0, CVMX_CIU_WDOGX(coreid) 167 */ 168 uasm_i_ld(&p, K0, 0x500, K0); 169 /* 170 * If bit one set handle the NMI as a watchdog event. 171 * otherwise transfer control to bootloader. 172 */ 173 uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader); 174 uasm_i_nop(&p); 175#endif 176 177 /* Clear Dcache so cvmseg works right. */ 178 uasm_i_cache(&p, 1, 0, 0); 179 180 /* Use K0 to do a read/modify/write of CVMMEMCTL */ 181 uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL); 182 /* Clear out the size of CVMSEG */ 183 uasm_i_dins(&p, K0, 0, 0, 6); 184 /* Set CVMSEG to its largest value */ 185 uasm_i_ori(&p, K0, K0, 0x1c0 | 54); 186 /* Store the CVMMEMCTL value */ 187 uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL); 188 189 /* Load the address of the second stage handler */ 190 UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2); 191 uasm_i_jr(&p, K0); 192 uasm_i_dmfc0(&p, K0, C0_DESAVE); 193 194#ifdef CONFIG_HOTPLUG_CPU 195 uasm_build_label(&l, p, label_enter_bootloader); 196 /* Jump to the bootloader and restore K0 */ 197 UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr); 198 uasm_i_jr(&p, K0); 199 uasm_i_dmfc0(&p, K0, C0_DESAVE); 200#endif 201 uasm_resolve_relocs(relocs, labels); 202 203 len = (int)(p - nmi_stage1_insns); 204 pr_debug("Synthesized NMI stage 1 handler (%d instructions).\n", len); 205 206 pr_debug("\t.set push\n"); 207 pr_debug("\t.set noreorder\n"); 208 for (i = 0; i < len; i++) 209 pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]); 210 pr_debug("\t.set pop\n"); 211 212 if (len > 32) 213 panic("NMI stage 1 handler exceeds 32 instructions, was %d\n", len); 214} 215 216static int cpu2core(int cpu) 217{ 218#ifdef CONFIG_SMP 219 return cpu_logical_map(cpu); 220#else 221 return cvmx_get_core_num(); 222#endif 223} 224 225static int core2cpu(int coreid) 226{ 227#ifdef CONFIG_SMP 228 return cpu_number_map(coreid); 229#else 230 return 0; 231#endif 232} 233 234/** 235 * Poke the watchdog when an interrupt is received 236 * 237 * @cpl: 238 * @dev_id: 239 * 240 * Returns 241 */ 242static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) 243{ 244 unsigned int core = cvmx_get_core_num(); 245 int cpu = core2cpu(core); 246 247 if (do_coundown) { 248 if (per_cpu_countdown[cpu] > 0) { 249 /* We're alive, poke the watchdog */ 250 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); 251 per_cpu_countdown[cpu]--; 252 } else { 253 /* Bad news, you are about to reboot. */ 254 disable_irq_nosync(cpl); 255 cpumask_clear_cpu(cpu, &irq_enabled_cpus); 256 } 257 } else { 258 /* Not open, just ping away... */ 259 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); 260 } 261 return IRQ_HANDLED; 262} 263 264/* From setup.c */ 265extern int prom_putchar(char c); 266 267/** 268 * Write a string to the uart 269 * 270 * @str: String to write 271 */ 272static void octeon_wdt_write_string(const char *str) 273{ 274 /* Just loop writing one byte at a time */ 275 while (*str) 276 prom_putchar(*str++); 277} 278 279/** 280 * Write a hex number out of the uart 281 * 282 * @value: Number to display 283 * @digits: Number of digits to print (1 to 16) 284 */ 285static void octeon_wdt_write_hex(u64 value, int digits) 286{ 287 int d; 288 int v; 289 for (d = 0; d < digits; d++) { 290 v = (value >> ((digits - d - 1) * 4)) & 0xf; 291 if (v >= 10) 292 prom_putchar('a' + v - 10); 293 else 294 prom_putchar('0' + v); 295 } 296} 297 298const char *reg_name[] = { 299 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 300 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 301 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 302 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 303}; 304 305/** 306 * NMI stage 3 handler. NMIs are handled in the following manner: 307 * 1) The first NMI handler enables CVMSEG and transfers from 308 * the bootbus region into normal memory. It is careful to not 309 * destroy any registers. 310 * 2) The second stage handler uses CVMSEG to save the registers 311 * and create a stack for C code. It then calls the third level 312 * handler with one argument, a pointer to the register values. 313 * 3) The third, and final, level handler is the following C 314 * function that prints out some useful infomration. 315 * 316 * @reg: Pointer to register state before the NMI 317 */ 318void octeon_wdt_nmi_stage3(u64 reg[32]) 319{ 320 u64 i; 321 322 unsigned int coreid = cvmx_get_core_num(); 323 /* 324 * Save status and cause early to get them before any changes 325 * might happen. 326 */ 327 u64 cp0_cause = read_c0_cause(); 328 u64 cp0_status = read_c0_status(); 329 u64 cp0_error_epc = read_c0_errorepc(); 330 u64 cp0_epc = read_c0_epc(); 331 332 /* Delay so output from all cores output is not jumbled together. */ 333 __delay(100000000ull * coreid); 334 335 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); 336 octeon_wdt_write_hex(coreid, 1); 337 octeon_wdt_write_string(" ***\r\n"); 338 for (i = 0; i < 32; i++) { 339 octeon_wdt_write_string("\t"); 340 octeon_wdt_write_string(reg_name[i]); 341 octeon_wdt_write_string("\t0x"); 342 octeon_wdt_write_hex(reg[i], 16); 343 if (i & 1) 344 octeon_wdt_write_string("\r\n"); 345 } 346 octeon_wdt_write_string("\terr_epc\t0x"); 347 octeon_wdt_write_hex(cp0_error_epc, 16); 348 349 octeon_wdt_write_string("\tepc\t0x"); 350 octeon_wdt_write_hex(cp0_epc, 16); 351 octeon_wdt_write_string("\r\n"); 352 353 octeon_wdt_write_string("\tstatus\t0x"); 354 octeon_wdt_write_hex(cp0_status, 16); 355 octeon_wdt_write_string("\tcause\t0x"); 356 octeon_wdt_write_hex(cp0_cause, 16); 357 octeon_wdt_write_string("\r\n"); 358 359 octeon_wdt_write_string("\tsum0\t0x"); 360 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); 361 octeon_wdt_write_string("\ten0\t0x"); 362 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); 363 octeon_wdt_write_string("\r\n"); 364 365 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); 366} 367 368static void octeon_wdt_disable_interrupt(int cpu) 369{ 370 unsigned int core; 371 unsigned int irq; 372 union cvmx_ciu_wdogx ciu_wdog; 373 374 core = cpu2core(cpu); 375 376 irq = OCTEON_IRQ_WDOG0 + core; 377 378 /* Poke the watchdog to clear out its state */ 379 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); 380 381 /* Disable the hardware. */ 382 ciu_wdog.u64 = 0; 383 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); 384 385 free_irq(irq, octeon_wdt_poke_irq); 386} 387 388static void octeon_wdt_setup_interrupt(int cpu) 389{ 390 unsigned int core; 391 unsigned int irq; 392 union cvmx_ciu_wdogx ciu_wdog; 393 394 core = cpu2core(cpu); 395 396 /* Disable it before doing anything with the interrupts. */ 397 ciu_wdog.u64 = 0; 398 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); 399 400 per_cpu_countdown[cpu] = countdown_reset; 401 402 irq = OCTEON_IRQ_WDOG0 + core; 403 404 if (request_irq(irq, octeon_wdt_poke_irq, 405 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) 406 panic("octeon_wdt: Couldn't obtain irq %d", irq); 407 408 cpumask_set_cpu(cpu, &irq_enabled_cpus); 409 410 /* Poke the watchdog to clear out its state */ 411 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); 412 413 /* Finally enable the watchdog now that all handlers are installed */ 414 ciu_wdog.u64 = 0; 415 ciu_wdog.s.len = timeout_cnt; 416 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 417 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); 418} 419 420static int octeon_wdt_cpu_callback(struct notifier_block *nfb, 421 unsigned long action, void *hcpu) 422{ 423 unsigned int cpu = (unsigned long)hcpu; 424 425 switch (action) { 426 case CPU_DOWN_PREPARE: 427 octeon_wdt_disable_interrupt(cpu); 428 break; 429 case CPU_ONLINE: 430 case CPU_DOWN_FAILED: 431 octeon_wdt_setup_interrupt(cpu); 432 break; 433 default: 434 break; 435 } 436 return NOTIFY_OK; 437} 438 439static void octeon_wdt_ping(void) 440{ 441 int cpu; 442 int coreid; 443 444 for_each_online_cpu(cpu) { 445 coreid = cpu2core(cpu); 446 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); 447 per_cpu_countdown[cpu] = countdown_reset; 448 if ((countdown_reset || !do_coundown) && 449 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { 450 /* We have to enable the irq */ 451 int irq = OCTEON_IRQ_WDOG0 + coreid; 452 enable_irq(irq); 453 cpumask_set_cpu(cpu, &irq_enabled_cpus); 454 } 455 } 456} 457 458static void octeon_wdt_calc_parameters(int t) 459{ 460 unsigned int periods; 461 462 timeout_sec = max_timeout_sec; 463 464 465 /* 466 * Find the largest interrupt period, that can evenly divide 467 * the requested heartbeat time. 468 */ 469 while ((t % timeout_sec) != 0) 470 timeout_sec--; 471 472 periods = t / timeout_sec; 473 474 /* 475 * The last two periods are after the irq is disabled, and 476 * then to the nmi, so we subtract them off. 477 */ 478 479 countdown_reset = periods > 2 ? periods - 2 : 0; 480 heartbeat = t; 481 timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8; 482} 483 484static int octeon_wdt_set_heartbeat(int t) 485{ 486 int cpu; 487 int coreid; 488 union cvmx_ciu_wdogx ciu_wdog; 489 490 if (t <= 0) 491 return -1; 492 493 octeon_wdt_calc_parameters(t); 494 495 for_each_online_cpu(cpu) { 496 coreid = cpu2core(cpu); 497 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); 498 ciu_wdog.u64 = 0; 499 ciu_wdog.s.len = timeout_cnt; 500 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ 501 cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); 502 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); 503 } 504 octeon_wdt_ping(); /* Get the irqs back on. */ 505 return 0; 506} 507 508/** 509 * octeon_wdt_write: 510 * @file: file handle to the watchdog 511 * @buf: buffer to write (unused as data does not matter here 512 * @count: count of bytes 513 * @ppos: pointer to the position to write. No seeks allowed 514 * 515 * A write to a watchdog device is defined as a keepalive signal. Any 516 * write of data will do, as we we don't define content meaning. 517 */ 518 519static ssize_t octeon_wdt_write(struct file *file, const char __user *buf, 520 size_t count, loff_t *ppos) 521{ 522 if (count) { 523 if (!nowayout) { 524 size_t i; 525 526 /* In case it was set long ago */ 527 expect_close = 0; 528 529 for (i = 0; i != count; i++) { 530 char c; 531 if (get_user(c, buf + i)) 532 return -EFAULT; 533 if (c == 'V') 534 expect_close = 1; 535 } 536 } 537 octeon_wdt_ping(); 538 } 539 return count; 540} 541 542/** 543 * octeon_wdt_ioctl: 544 * @file: file handle to the device 545 * @cmd: watchdog command 546 * @arg: argument pointer 547 * 548 * The watchdog API defines a common set of functions for all 549 * watchdogs according to their available features. We only 550 * actually usefully support querying capabilities and setting 551 * the timeout. 552 */ 553 554static long octeon_wdt_ioctl(struct file *file, unsigned int cmd, 555 unsigned long arg) 556{ 557 void __user *argp = (void __user *)arg; 558 int __user *p = argp; 559 int new_heartbeat; 560 561 static struct watchdog_info ident = { 562 .options = WDIOF_SETTIMEOUT| 563 WDIOF_MAGICCLOSE| 564 WDIOF_KEEPALIVEPING, 565 .firmware_version = 1, 566 .identity = "OCTEON", 567 }; 568 569 switch (cmd) { 570 case WDIOC_GETSUPPORT: 571 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; 572 case WDIOC_GETSTATUS: 573 case WDIOC_GETBOOTSTATUS: 574 return put_user(0, p); 575 case WDIOC_KEEPALIVE: 576 octeon_wdt_ping(); 577 return 0; 578 case WDIOC_SETTIMEOUT: 579 if (get_user(new_heartbeat, p)) 580 return -EFAULT; 581 if (octeon_wdt_set_heartbeat(new_heartbeat)) 582 return -EINVAL; 583 /* Fall through. */ 584 case WDIOC_GETTIMEOUT: 585 return put_user(heartbeat, p); 586 default: 587 return -ENOTTY; 588 } 589} 590 591/** 592 * octeon_wdt_open: 593 * @inode: inode of device 594 * @file: file handle to device 595 * 596 * The watchdog device has been opened. The watchdog device is single 597 * open and on opening we do a ping to reset the counters. 598 */ 599 600static int octeon_wdt_open(struct inode *inode, struct file *file) 601{ 602 if (test_and_set_bit(0, &octeon_wdt_is_open)) 603 return -EBUSY; 604 /* 605 * Activate 606 */ 607 octeon_wdt_ping(); 608 do_coundown = 1; 609 return nonseekable_open(inode, file); 610} 611 612/** 613 * octeon_wdt_release: 614 * @inode: inode to board 615 * @file: file handle to board 616 * 617 * The watchdog has a configurable API. There is a religious dispute 618 * between people who want their watchdog to be able to shut down and 619 * those who want to be sure if the watchdog manager dies the machine 620 * reboots. In the former case we disable the counters, in the latter 621 * case you have to open it again very soon. 622 */ 623 624static int octeon_wdt_release(struct inode *inode, struct file *file) 625{ 626 if (expect_close) { 627 do_coundown = 0; 628 octeon_wdt_ping(); 629 } else { 630 pr_crit("octeon_wdt: WDT device closed unexpectedly. WDT will not stop!\n"); 631 } 632 clear_bit(0, &octeon_wdt_is_open); 633 expect_close = 0; 634 return 0; 635} 636 637static const struct file_operations octeon_wdt_fops = { 638 .owner = THIS_MODULE, 639 .llseek = no_llseek, 640 .write = octeon_wdt_write, 641 .unlocked_ioctl = octeon_wdt_ioctl, 642 .open = octeon_wdt_open, 643 .release = octeon_wdt_release, 644}; 645 646static struct miscdevice octeon_wdt_miscdev = { 647 .minor = WATCHDOG_MINOR, 648 .name = "watchdog", 649 .fops = &octeon_wdt_fops, 650}; 651 652static struct notifier_block octeon_wdt_cpu_notifier = { 653 .notifier_call = octeon_wdt_cpu_callback, 654}; 655 656 657/** 658 * Module/ driver initialization. 659 * 660 * Returns Zero on success 661 */ 662static int __init octeon_wdt_init(void) 663{ 664 int i; 665 int ret; 666 int cpu; 667 u64 *ptr; 668 669 /* 670 * Watchdog time expiration length = The 16 bits of LEN 671 * represent the most significant bits of a 24 bit decrementer 672 * that decrements every 256 cycles. 673 * 674 * Try for a timeout of 5 sec, if that fails a smaller number 675 * of even seconds, 676 */ 677 max_timeout_sec = 6; 678 do { 679 max_timeout_sec--; 680 timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * max_timeout_sec) >> 8; 681 } while (timeout_cnt > 65535); 682 683 BUG_ON(timeout_cnt == 0); 684 685 octeon_wdt_calc_parameters(heartbeat); 686 687 pr_info("octeon_wdt: Initial granularity %d Sec.\n", timeout_sec); 688 689 ret = misc_register(&octeon_wdt_miscdev); 690 if (ret) { 691 pr_err("octeon_wdt: cannot register miscdev on minor=%d (err=%d)\n", 692 WATCHDOG_MINOR, ret); 693 goto out; 694 } 695 696 /* Build the NMI handler ... */ 697 octeon_wdt_build_stage1(); 698 699 /* ... and install it. */ 700 ptr = (u64 *) nmi_stage1_insns; 701 for (i = 0; i < 16; i++) { 702 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); 703 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]); 704 } 705 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); 706 707 cpumask_clear(&irq_enabled_cpus); 708 709 for_each_online_cpu(cpu) 710 octeon_wdt_setup_interrupt(cpu); 711 712 register_hotcpu_notifier(&octeon_wdt_cpu_notifier); 713out: 714 return ret; 715} 716 717/** 718 * Module / driver shutdown 719 */ 720static void __exit octeon_wdt_cleanup(void) 721{ 722 int cpu; 723 724 misc_deregister(&octeon_wdt_miscdev); 725 726 unregister_hotcpu_notifier(&octeon_wdt_cpu_notifier); 727 728 for_each_online_cpu(cpu) { 729 int core = cpu2core(cpu); 730 /* Disable the watchdog */ 731 cvmx_write_csr(CVMX_CIU_WDOGX(core), 0); 732 /* Free the interrupt handler */ 733 free_irq(OCTEON_IRQ_WDOG0 + core, octeon_wdt_poke_irq); 734 } 735 /* 736 * Disable the boot-bus memory, the code it points to is soon 737 * to go missing. 738 */ 739 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); 740} 741 742MODULE_LICENSE("GPL"); 743MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>"); 744MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver."); 745module_init(octeon_wdt_init); 746module_exit(octeon_wdt_cleanup); 747