| 9918ceafd4a9e013572e03983f528017c29bb1cb |
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26-Jan-2012 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
ARM: at91: code removal of CAP9 SoC
Following removal announce and addition to feature-removal-schedule.txt,
here is the actual source code deletion for Atmel CAP9 family.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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| cfa5a1fe7e65bacdee59d5df60a9f44b0c030532 |
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13-Oct-2011 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
ARM: at91: add ioremap_registers entry point to soc setup
this will allow to ioremap the register of the PIT, PMC and others
and make the code soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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| 51ddec7617bd0d4c73c44a8862faac5d7d97eb03 |
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24-Apr-2011 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
at91: move register clocks to soc generic init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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| 465393749da3a3229f6067246c7e8f97f7cc833d |
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24-Apr-2011 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
at91: move clock subsystem init to soc generic init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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| 8c3583b634d5705d8f604c0d9392bc273d19c256 |
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23-Apr-2011 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
at91: use structure to store the current soc
instead of reading the registers everytime
the current implementation respect the following constrain:
- allow 1 to n soc to be enabled
- allow to have a virtual cpu type and subtype
- always detect the cpu type and subtype and report it
- detect if the soc support is enabled
- prepare for sysfs export support
- drop soc specific code via compiler when the soc not enabled
(via cpu_is_xxx)
Today if we read the exid we will have the same value for 9g35 and 9m11
and we will need to check the cidr too
with the new implementation we just need to check the soc subtype
this will also allow to have specific virtual subtype for rm9200 which the
board will have to specify via at91rm9200_set_type(int) as we have no way to
detect it.
this implementation is inspired by the SH cpu detection support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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| 92100c12ca1bc5f347ff41c1413f9db07c4d276c |
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23-Apr-2011 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
at91: factorize at91 interrupts init to soc
they are the same except the default priority
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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| 21d08b9d5536ac418bbce4f419fe2b528b7ddf31 |
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23-Apr-2011 |
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
at91: introduce commom AT91_BASE_SYS
On all at91 except rm9200 and x40 have the System Controller starts
at address 0xffffc000 and has a size of 16KiB.
On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
at 0xfffff000
This patch removes the individual definitions of AT91_BASE_SYS and
replaces them with a common version at base 0xfffffc000 and size 16KiB
and map the same memory space
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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