| b0e7808d548ea1d857216d31d63078411203a116 |
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01-Mar-2011 |
Stepan Moskovchenko <stepanm@codeaurora.org> |
msm: iommu: Don't read from write-only registers
Don't read from V2Pxx command registers when doing
iova-to-phys operations. These registers are write-only and
reading the value before modifying the VA bits is
unnecessary.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
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| 2e8c8ba98376459e73d03a285f5d3406b630ea2d |
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25-Feb-2011 |
Stepan Moskovchenko <stepanm@codeaurora.org> |
msm: iommu: Use ASID tagging instead of VMID tagging
Use ASID tags in the TLB instead of VMID tags in
preparation for changes to the secure environment.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
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| 08bd6839783319085ee0db4c888534e626225774 |
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16-Nov-2010 |
Stepan Moskovchenko <stepanm@codeaurora.org> |
msm: iommu: Definitions for extended memory attributes
Add the register field definitions and memory attribute
definitions that will be needed to support IOMMU
transactions with cache-coherent memory access.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
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| 0720d1f052dc1576396a39b327da6e60082c4efa |
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25-Aug-2010 |
Stepan Moskovchenko <stepanm@codeaurora.org> |
msm: Add MSM IOMMU support
Add support for the IOMMUs found on the upcoming Qualcomm
MSM8x60 chips. These IOMMUs allow virtualization of the
address space used by most of the multimedia cores on these
chips.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
|