| e02db0aa3e1976ae4e23a66077d252a2f3ba74c7 |
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08-Feb-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Handle TLB skip size dynamically
This patch fix the problem with rootfs on JFFS2 with early printk
console turned on.
The origin version used TLB63 for temporary early printk mapping.
The code expect that kernel is not able to use all 64 TLB entries
till early printk console is remapped by ioremap. After that
temporary mapping on TLB63 is silently lost.
This expectation give the opportunity to have early console pretty
early.
Microblaze systems with JFFS2 rootfs with early printk console turned on
used more than 64 TLB entries before kernel can remap early console.
Based on that kernel does access to bad area because early printk mapping
is rewritten.
This patch introduces tlb_skip variable which dynamically stores number
of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1
should be skipped.
MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start.
They can be used for user purpose.
TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID).
Also clean TLBLO when kernel starts.
For specific kernel sizes kernel can use just one TLB. Detect this case
and use the second TLB for general purpose.
Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE.
Export tlb_skip size through debugfs.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 1451d1d88b9aa32ac9ee54180239e9b34b6f9e86 |
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04-Apr-2011 |
Michal Simek <monstr@monstr.eu> |
microblaze: Introduce TLB skip size
TLB skip size direct how many TLBs is skipped.
Currently TLB0 and TLB1 are used for Linux kernel mapping
that's why their are skipped.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| c11389406f19e4bddc7b347e5259aebda02b23f1 |
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20-May-2011 |
Michal Simek <monstr@monstr.eu> |
microblaze: Fix unaligned value saving to the stack for system with MMU
Several registers weren't saved correctly to the stack.
Unaligned expection for system with MMU stores
value in ex_tmp_data_loc_X address which is load to registers r3.
The next step is to move this value from r3 to a destination
register which caused unaligned exception. For several registers
this value was directly moved to the register.
For example for r28:
by "or r28, r0, r3"
but register r28 was rewritten when kernel returns from exception
handler by value saved on stack.
This patch changed r3 saving to the correct address on the stack.
For example for r28:
by "swi r3, r1, 4 * 28"
When kernel returns from the exception handler, correct value is restored.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| cd3415779bdb13e3daaf13965c89d286a0cf0480 |
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01-Feb-2011 |
Michal Simek <monstr@monstr.eu> |
microblaze: Do not use "la" pseudo instruction - use addik instead
"la" pseudo instruction is only translation to "addik".
Use directly "addik" which is described in the MB reference guide.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 6e83557c38b40d6e9d1c82ad0ae59d8e5db9c50c |
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31-Jan-2011 |
Michal Simek <monstr@monstr.eu> |
microblaze: Remove r0_ram pointer and PTO alignment
r0_ram pool was used for saving/restoring register
content if hw exception happen. This poll was replaced by
pt_pool_space with PT_SIZE size.
Based on this change SAVE_STATE_ARG_SPACE was removed which
caused that PTO offset is zero that's why is also removed.
r0_ram space was used as scratchpad by v850. In early
Microblaze Linux developing phase was this part of code
blindly copied.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| c06b3a068223cb885d85ac4f6c31e870ca2b5aac |
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31-Jan-2011 |
Michal Simek <monstr@monstr.eu> |
microblaze: Do not use r0_ram space for hw exception debugging
Remove hw exception counting space from r0_ram. Use special
exception_debug_table poll for exception statistic.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 9c749e177ccc0b3ee9589425c7255079e7a726fc |
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28-Jan-2011 |
Michal Simek <monstr@monstr.eu> |
microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1
Unaligned code use shift for finding register operand.
There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1
by
ori rD, r0, (1 << imm); \
idivu rD, rD, rA
but if rD is equal rA then ori instruction rewrite value which
should be devide.
The patch remove this macro which use idivu instruction because
idivu takes 32/34 cycles. The highest shifting is 20 which takes
20 cycles.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| e3288f310111f7d18c323d95ae998765dee8c825 |
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29-Dec-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Fix unaligned exception for little endian platform
Half word unaligned accesses need to be fixed.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| ce3266c047389443d5f433d605c769e878cbe46e |
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27-Apr-2010 |
Steven J. Magnani <steve@digidescorp.com> |
microblaze: Add stack unwinder
Implement intelligent backtracing by searching for stack frame creation,
and emitting only return addresses. Use print_hex_dump() to display the
entire binary kernel stack.
Limitation: MMU kernels are not currently able to trace beyond a system trap
(interrupt, syscall, etc.). It is the intent of this patch to provide
infrastructure that can be extended to add this capability later.
Changes from V1:
* Removed checks in find_frame_creation() that prevented location of the frame
creation instruction in heavily optimized code
* Various formatting/commenting/file location tweaks per review comments
* Dropped Kconfig option to enable STACKTRACE as something logically separate
Signed-off-by: Steven J. Magnani <steve@digidescorp.com>
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| 3765d6958dfff34a15588e23c5d1274e1f6ba200 |
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22-Mar-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Use instruction with delay slot
Sync labels.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| bd1637d63e82aaf732ffbe907ba887fa12e82df4 |
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19-Mar-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Remove additional resr and rear loading
RESR and REAR uses the same regs in whole file.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| b175bcfe31cba846d8bfa35a3a4820667f7af383 |
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19-Mar-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Change register usage for ESR and EAR
This change synchronize register usage in code.
ESR = R4
EAR = R3
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 7a6bbdc9304b45cc759e03623cbe63d81aff7337 |
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22-Mar-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Prepare work for optimization in exception code
Any sync branch must follow mts instructions not mfs.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| 708e7153d6fc4d2e5fe15c6ccc5d2907fe8a9c8d |
|
18-Mar-2010 |
Michal Simek <monstr@monstr.eu> |
microblaze: Add DEBUG option
Disable debug option in asm code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 131e4e97bfee809dc64febe8accef2f042a92722 |
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28-Sep-2009 |
Michal Simek <monstr@monstr.eu> |
microblaze: Clear sticky FSR register after saving it to func parametr
Previous patch d63678d607d0e37ec7abe5ceb545d7e8aab956a4 clear
it for noMMU kernel. This one do it for MMU.
Correct noMMU version
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 71b23d547b5a06f49acacaf742ebf1a85673f8d1 |
|
14-Sep-2009 |
John Williams <john.williams@petalogix.com> |
microblaze: Clear sticky FSR register after generating exception signals
FSR is sticky, so after the userspace exception/signal generation, clear
it ready for next time.
Signed-off-by: John Williams <john.williams@petalogix.com>
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| ac854ff1fc779101ff1989c3a20c1f238a2b5f3a |
|
17-Sep-2009 |
Michal Simek <monstr@monstr.eu> |
microblaze: Save and restore msr in hw exception
I thought that this part of code could be removed because just
save and restore MSR but any code can't change it. But seems to
that any part of code works with this information.
This patch solved problem with allocation.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 3863dbceac7e69642b95f43de1c12c6236fdbe5b |
|
21-Jul-2009 |
Michal Simek <monstr@monstr.eu> |
microblaze: Support unaligned address for put/get_user macros
This patch add support for cases where load/store instruction
in put/get_user macro gets unaligned pointer to data and this
address is not valid. I prevent all cases which can failed.
I had to disable first stage of unaligned handler which is used
only for noMMU kernel and the whole work is done when interrupt
is enabled.
You have enable HW support for detect unaligned access in Microblaze.
This patch fixed three LTP tests:
getpeername01, getsockname01, socketpair01
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| 7db29dde731db02143418cfa008b7b77ccb2fa57 |
|
26-May-2009 |
Michal Simek <monstr@monstr.eu> |
microblaze_mmu_v2: Update exception handling - MMU exception
Signed-off-by: Michal Simek <monstr@monstr.eu>
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| c4df4bc155bbe18fb91800bb9d29499a4fb211ad |
|
27-Mar-2009 |
Michal Simek <monstr@monstr.eu> |
microblaze_v8: exception handling
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
|