History log of /arch/mips/include/asm/octeon/cvmx-smix-defs.h
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
aa32a955ae46d4117e880417c89a2efcc88579c2 08-Oct-2010 David Daney <ddaney@caviumnetworks.com> MIPS: Octeon: Update register definitions for CN63XX chips

The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together. This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/include/asm/octeon/cvmx-smix-defs.h
25d967b72a92d72b6e0263a0337dfc940bd6c044 14-Oct-2009 David Daney <ddaney@caviumnetworks.com> NET: Add driver for Octeon MDIO buses.

The Octeon SOC has two types of Ethernet ports, each type with its own
driver. However, the PHYs for all the ports are controlled by a
common MDIO bus. Because the mdio driver is not associated with a
particular driver, but is instead a system level resource, we create s
stand-alone driver for it.

As for the driver, we put the register definitions in
arch/mips/include/asm/octeon where most of the other Octeon register
definitions live. This is a platform driver with the platform device
for "mdio-octeon" being registered in the platform startup code.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/include/asm/octeon/cvmx-smix-defs.h