| b81947c646bfefdf98e2fde5d7d39cbbda8525d4 |
|
28-Mar-2012 |
David Howells <dhowells@redhat.com> |
Disintegrate asm/system.h for MIPS
Disintegrate asm/system.h for MIPS.
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
cc: linux-mips@linux-mips.org
/arch/mips/mm/tlb-r4k.c
|
| 39b741431af7f6f46b2e0e7f7f13ea2351fb4a5f |
|
11-Jan-2012 |
Ralf Baechle <ralf@linux-mips.org> |
Merge branch 'next/generic' into mips-for-linux-next
|
| d7a887a73dec6c387b02a966a71aac767bbd9ce6 |
|
11-Jan-2012 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Delete unused function add_temporary_entry.
Only available for R4000 style TLBs anyway and proper ordering of
initialization code made this crude interface unncecessary.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| f467e4bfb50ca6af042f1b19b3556bd4aca854c3 |
|
11-Jan-2012 |
Hillf Danton <dhillf@gmail.com> |
MIPS: Flush huge TLB
When flushing TLB, if @vma is backed by huge page, we could flush huge
TLB, due to that huge page is defined to be far from normal page.
Signed-off-by: Hillf Danton <dhillf@gmail.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: "Jayachandran C." <jayachandranc@netlogicmicro.com>
Patchwork: https://patchwork.linux-mips.org/patch/2825/
Signed-off-by: David Daney <david.daney@cavium.com>
Acked-by: Hillf Danton <dhillf@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/3114/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 3d18c98367eac23555ea4887c4f570423474eeaf |
|
28-Nov-2011 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Fix Jazz 64-bit build error.
Move add_wired_entry to its own header file from where it will be
always included. Patch up other users of add_wired_entry to also include
the header as needed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 694b8c35e95078bfe1cb1388bf0cf7942e32f009 |
|
02-Aug-2011 |
Manuel Lauss <manuel.lauss@googlemail.com> |
MIPS: Remove __init from add_wired_entry()
For Alchemy-PCI I need to add a wired entry after resuming from RAM;
remove the __init from add_wired_entry() so that this actually works.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2684/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 79add6277396b91c638f16eb2f1338badc47760d |
|
04-Apr-2011 |
Justin P. Mattock <justinmattock@gmail.com> |
update David Miller's old email address
Signed-off-by: Justin P. Mattock <justinmattock@gmail.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
/arch/mips/mm/tlb-r4k.c
|
| 6dd9344cfc41bcc60a01cdc828cb278be7a10e01 |
|
11-Feb-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Implement Read Inhibit/eXecute Inhibit
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit
(XI) bits in the page tables work. The upper two bits of EntryLo{0,1}
are RI and XI when the feature is enabled in the PageGrain register.
SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to
64-bit systems by continuing to place the RI and XI bits in the top of
EntryLo even when EntryLo is 64-bits wide.
Because we need to carry the RI and XI bits in the PTE, the layout of
the PTE is changed. There is a two instruction overhead in the TLB
refill hot path to get the EntryLo bits into the proper position.
Also the TLB load exception has to probe the TLB to check if RI or XI
caused the exception.
Also of note is that the layout of the PTE bits is done at compile and
runtime rather than statically. In the 32-bit case this allows for
the same number of PFN bits as before the patch as the _PAGE_HUGE is
not supported in 32-bit kernels (we have _PAGE_NO_EXEC and
_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).
The patch is tested on Cavium Octeon+, but should also work on 32-bit
systems with the Smart-MIPS ASE.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/952/
Patchwork: http://patchwork.linux-mips.org/patch/956/
Patchwork: http://patchwork.linux-mips.org/patch/962/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| b66bb6090d9aa36931911e34d3f069932934b6fe |
|
03-Feb-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Remove #if 0 r4k_update_mmu_cache_hwbug
The function is #if 0ed out. There are no other occurrences of its
name in the tree. It is safe to remove.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/936/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 2a880986d899f556f5a327bc77cc8760d5bb9c64 |
|
22-Jan-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Remove probe_tlb().
The function probe_tlb() only does anything for processors that are
not PRID_COMP_LEGACY. This is precisely the set of processors for
which decode_configs() is called to do identical tlbsize probing
calculations. Therefore probe_tlb() is completely redundant and may
be removed.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/865/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 982f6ffeeed5ef6104cfd72e517ff9e7a9270fda |
|
17-Sep-2009 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Remove useless zero initializations.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 631330f5847b3f8a7ea67d689e9f7c56833ccaa6 |
|
19-Jun-2009 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.
Some of the were relying into smp.h being dragged in by another header
which of course is fragile. <asm/cpu-info.h> uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| fd062c847a8cea2821347d7e18165dfa658f7dce |
|
28-May-2009 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: TLB support for hugetlbfs.
The TLB handlers need to check for huge pages and give them special
handling. Huge pages consist of two contiguous sub-pages of physical
memory.
* Loading entrylo0 and entrylo1 need to be handled specially.
* The page mask must be set for huge pages and then restored after
writing the TLB entries.
* The PTE for huge pages resides in the PMD, we halt traversal of the
tables there.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| a5e696e5d0f1377ff6beb10d2f40edb6a3d1de18 |
|
20-May-2009 |
Greg Ungerer <gerg@snapgear.com> |
MIPS: 64-bit: Fix system lockup.
The address range size calculation inside local_flush_tlb_kernel_range()
is being truncated by a too small size variable holder on 64-bit systems.
The truncated size can result in an erroneous tlbsize check that means we
sit spinning inside a loop trying to flush a hige number of TLB entries.
This is for all intents and purposes a system hang. Fix by using an
appropriately sized valiable to hold the size.
[Ralf: Greg's original patch submission identified the issue and fixed one
instance in tlb-r4k.c but there there were several more. For consistency
I also modified tlb-r3k.c even though that file is only used on 32-bit.]
Signed-off-by: Greg Ungerer <gerg@snapgear.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| cde15b5927fea3e1b4de0b277008cf273d8b000b |
|
07-Jan-2009 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Only write c0_framemask on CPUs which have this register.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 962f480e0f9024ecdcfe2ba1d216c038ee328ced |
|
19-Sep-2007 |
Chris Dearman <chris@mips.com> |
[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 234fcd1484a66158b561b36b421547f0ab85fee9 |
|
08-Mar-2008 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| a7c2996e41ada10d504050863bbc318f5ed2a0c2 |
|
29-Feb-2008 |
Thiemo Seufer <ths@networkno.de> |
[MIPS] Fix typo in comment
We support now other page sizes as well.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 49a89efbbbcc178a39555c43bd59a7593c429664 |
|
12-Oct-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 2a21c7300b53b744d16903256a172d9cbcfdd03e |
|
06-Jun-2007 |
Fuxin Zhang <zhangfx@lemote.com> |
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 2806ccd7ad9073f4f1a065b5672d7592e7838e97 |
|
19-Dec-2006 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Delete duplicate call to load_irq_save.
This call may have resulted to local_tlb_flush_range returning with
interrupts disabled resulting in excessive interrupt latency.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 432bef2a31668a0562e5738eaa59a43854f26567 |
|
08-Sep-2006 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Replace BARRIER with more appropriate hazard barrier.
This is the unchanged part 2 of Chris' hazard cleanup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 6ab3d5624e172c553004ecc862bfeac16d9d68b7 |
|
30-Jun-2006 |
Jörn Engel <joern@wohnheim.fh-wedel.de> |
Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
/arch/mips/mm/tlb-r4k.c
|
| 5deee2dbf495b2693629f7e8f846483432096278 |
|
15-May-2006 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] Remove prototype for non-existing function.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 41c594ab65fc89573af296d192aa5235d09717ab |
|
05-Apr-2006 |
Ralf Baechle <ralf@linux-mips.org> |
[MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| c6281edb1d5e307f056fff0e174f60fa6133adc5 |
|
14-Mar-2006 |
Thiemo Seufer <ths@networkno.de> |
[MIPS] Kill tlb-andes.c.
Basically identical to c-r4k.c, so maintaining one is really enough.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 6e760c8dae7d6c47eff011dd4aad53c94d30494b |
|
06-Jul-2005 |
Ralf Baechle <ralf@linux-mips.org> |
Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 172546bf601356f94f8018af7908a9b7c1c4915c |
|
02-Apr-2005 |
Thiemo Seufer <ths@networkno.de> |
Fix race conditions for read_c0_entryhi. Remove broken ASID masks in
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| c6e8b587718c486b55c2ebecc6de231a30beba35 |
|
10-Feb-2005 |
Ralf Baechle <ralf@linux-mips.org> |
Update MIPS to use the 4-level pagetable code thereby getting rid of
the compacrapability headers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 304429915dad26ccf212d63ea1f18be36e3188e2 |
|
02-Feb-2005 |
Maciej W. Rozycki <macro@linux-mips.org> |
Formatting fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/mm/tlb-r4k.c
|
| 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 |
|
17-Apr-2005 |
Linus Torvalds <torvalds@ppc970.osdl.org> |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
/arch/mips/mm/tlb-r4k.c
|