| 595789a192f141fde48d8f9ed9d6071be2e52168 |
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08-Dec-2011 |
David Daney <david.daney@cavium.com> |
MIPS: Octeon: Add support for OCTEON II PCIe
OCTEON II SOCs have a different PCIe implementation than is present in
OCTEON Plus.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2985/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/pci/pcie-octeon.c
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| b595076a180a56d1bb170e6eceda6eb9d76f4cd3 |
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01-Nov-2010 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
/arch/mips/pci/pcie-octeon.c
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| b93b2abce497873be97d765b848e0a955d29f200 |
|
01-Oct-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Octeon: Rewrite DMA mapping functions.
All Octeon chips can support more than 4GB of RAM. Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.
Enable the swiotlb code to handle the cases where a device cannot directly
do DMA. This is a complete rewrite of the Octeon DMA mapping code.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/pci/pcie-octeon.c
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| 2b5987abaf2dd6c3934e0376b7d9f64411cdcf03 |
|
04-Aug-2010 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Octeon: Allow more than 3.75GB of memory with PCIe
We reserve the 3.75GB - 4GB region of PCIe address space for device to
device transfers, making the corresponding physical memory under
direct mapping unavailable for DMA.
To allow for PCIe DMA to all physical memory we map this chunk of
physical memory with BAR1. Because of the resulting discontinuity in
the mapping function, we remove a page of memory at each end of the
range so multi-page DMA buffers can never be allocated that span the
range.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1535/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/pci/pcie-octeon.c
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| 838c05705ef8c110037a713526bb18762db0a241 |
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15-Jul-2009 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Octeon PCIe: Make hardware and software bus numbers match.
Some SiliconImage PCIe SATA controlers are not detected when the bus
numbers differ.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/pci/pcie-octeon.c
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| 01a6221a6a51ec47b9ae3ed42c396f98dd488c7e |
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30-Jun-2009 |
David Daney <ddaney@caviumnetworks.com> |
MIPS: Reorganize Cavium OCTEON PCI support.
Move the cavium PCI files to the arch/mips/pci directory. Also cleanup
comment formatting and code layout. Code from pci-common.c, was moved
into other files.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
/arch/mips/pci/pcie-octeon.c
|