1c80f22f8d809a9a9024aad7a5bd093f078e77cf |
28-Mar-2012 |
David Howells <dhowells@redhat.com> |
Disintegrate asm/system.h for MN10300 Disintegrate asm/system.h for MN10300. Signed-off-by: David Howells <dhowells@redhat.com> cc: linux-am33-list@redhat.com
ault.c
nit.c
isalignment.c
gtable.c
lb-smp.c
|
60063497a95e716c9a689af3be2687d261f115b4 |
27-Jul-2011 |
Arun Sharma <asharma@fb.com> |
atomic: use <linux/atomic.h> This allows us to move duplicated code in <asm/atomic.h> (atomic_inc_not_zero() for now) to <linux/atomic.h> Signed-off-by: Arun Sharma <asharma@fb.com> Reviewed-by: Eric Dumazet <eric.dumazet@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Miller <davem@davemloft.net> Cc: Eric Dumazet <eric.dumazet@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
2e65d1f6eecc176ba1341541b5f41edd7eb4346a |
06-Jun-2011 |
David Howells <dhowells@redhat.com> |
MN10300: Fix one of the kernel debugger cacheflush variants One of the kernel debugger cacheflush variants escaped proper testing. Two of the labels are wrong, being derived from the code that was copied to construct the variant. The first label results in the following assembler message: AS arch/mn10300/mm/cache-dbg-flush-by-reg.o arch/mn10300/mm/cache-dbg-flush-by-reg.S: Assembler messages: arch/mn10300/mm/cache-dbg-flush-by-reg.S:123: Error: symbol `debugger_local_cache_flushinv_no_dcache' is already defined And the second label results in the following linker message: arch/mn10300/mm/built-in.o:(.text+0x1d39): undefined reference to `mn10300_local_icache_inv_range_reg_end' arch/mn10300/mm/built-in.o:(.text+0x1d39): relocation truncated to fit: R_MN10300_PCREL16 against undefined symbol `mn10300_local_icache_inv_range_reg_end' To test this file the following configuration pieces must be set: CONFIG_AM34=y CONFIG_MN10300_CACHE_WBACK=y CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG=y CONFIG_MN10300_CACHE_MANAGE_BY_REG=y CONFIG_AM34_HAS_CACHE_SNOOP=n Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ache-dbg-flush-by-reg.S
|
8ea9716fd6aa761482caa5d4d64b256ed07ac09f |
25-May-2011 |
KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> |
mn10300: convert old cpumask API into new one Adapt to the new API. We plan to remove old cpumask APIs later. Thus this patch converts them into the new one. Signed-off-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: David Howells <dhowells@redhat.com> Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Cc: Hugh Dickins <hughd@google.com> Cc: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ache-smp.c
lb-smp.c
|
1c395176962176660bb108f90e97e1686cfe0d85 |
25-May-2011 |
Peter Zijlstra <a.p.zijlstra@chello.nl> |
mm: now that all old mmu_gather code is gone, remove the storage Fold all the mmu_gather rework patches into one for submission Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Reported-by: Hugh Dickins <hughd@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David Miller <davem@davemloft.net> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Jeff Dike <jdike@addtoit.com> Cc: Richard Weinberger <richard@nod.at> Cc: Tony Luck <tony.luck@intel.com> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: Mel Gorman <mel@csn.ul.ie> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Nick Piggin <npiggin@kernel.dk> Cc: Namhyung Kim <namhyung@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
nit.c
|
67ddb4052daac9d449caf2643ac365d42a04219a |
18-Mar-2011 |
David Howells <dhowells@redhat.com> |
MN10300: Create generic kernel debugger hooks Create generic kernel debugger hooks in the MN10300 arch and make gdbstub use them. This is a preparation for KGDB support. Signed-off-by: David Howells <dhowells@redhat.com>
ault.c
|
7f386ac3272e057fbf51e5b5712fad1a80e77125 |
18-Mar-2011 |
David Howells <dhowells@redhat.com> |
MN10300: Create general kernel debugger cache flushing Create general kernel debugger cache flushing for MN10300 and get rid of the old stuff that gdbstub was using. Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
akefile
ache-dbg-flush-by-reg.S
ache-dbg-flush-by-tag.S
ache-dbg-inv-by-reg.S
ache-dbg-inv-by-tag.S
ache-dbg-inv.S
ache-flush-by-tag.S
ache-inv-by-reg.S
ache-inv-by-tag.S
|
b75bb2365d50f73c09e42cf2de07f5805a3988ea |
18-Mar-2011 |
David Howells <dhowells@redhat.com> |
MN10300: The icache invalidate functions should disable the icache first The icache invalidate functions should disable the icache on AM33 and wait for it to quiesce before attempting to invalidate it, and should then wait for it to quiesce again before reenabling it, but on AM34 they should invalidate directly. The same goes for the dcache invalidation, but this isn't used much. Whilst we're at it, this can be wrapped in assembler macros to remove duplicate code. The AM33 manual states that: An operation that invalidates the cache, switches the writing mode, or changes the way mode must be performed after disabling the cache, checking the busy bit, and confirming that the cache is not in operation. for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec 2.8.3.1.1] but the example code there suggests that it is. Whilst the AM34 manual states that the cache must be disabled for both the icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware engineers say the manual is wrong and that disabling the caches for invalidation is wrong. Furthermore, they say that disabling the caches on the AM34 whilst running an SMP kernel can lead to incoherency between the various CPU caches and should thus be avoided. Signed-off-by: David Howells <dhowells@redhat.com>
ache-inv-by-reg.S
ache-inv-by-tag.S
ache.inc
|
dcca52c21e44aa69713390d6872c425b21df3abe |
14-Mar-2011 |
David Howells <dhowells@redhat.com> |
MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not exist The invalidate-only versions of flush_icache_*range() are trying sending the SMP_ICACHE_INV_FLUSH_RANGE IPI command in SMP kernels when they should be sending SMP_ICACHE_INV_RANGE as the former does not exist. Signed-off-by: David Howells <dhowells@redhat.com>
ache-inv-icache.c
|
5a226c6f5c374a0d565dac609907085b944979b5 |
27-Oct-2010 |
Mark Salter <msalter@redhat.com> |
MN10300: Map userspace atomic op regs as a vmalloc page The AM34 processor has an atomic operation that's the equivalent of LL/SC on other architectures. However, rather than being done through a pair of instructions, it's driven by writing to a pair of memory-mapped CPU control registers. One set of these registers (AARU/ADRU/ASRU) is available for use by userspace, but for userspace to access them a PTE must be set up to cover the region. This is done by dedicating the first vmalloc region page to this purpose, setting the permissions on its PTE such that userspace can access the page. glibc is hardcoded to expect the registers to be there. The way atomic ops are done through these registers is straightforward: (1) Write the address of the word you wish to access into AARU. This causes the CPU to go and fetch that word and load it into ADRU. The status bits are also cleared in ASRU. (2) The current data value is read from the ADRU register and modified. (3) To alter the data in RAM, the revised data is written back to the ADRU register, which causes the CPU to attempt to write it back. (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch), ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then must be checked to confirm that the operation wasn't aborted. If any of the watches have been set to true, the operation was aborted. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
nit.c
|
368dd5acd154b09c043cc4392a74da01599b37d5 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: And Panasonic AM34 subarch and implement SMP Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
ault.c
|
965ea4bbb9ae926358273368144ba838c561bc38 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: SMP TLB flushing Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
akefile
lb-smp.c
|
dccbf4853a31a3f774f38c402209d23388d99f52 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
lb-mn10300.S
|
a9bc60ebfd5766ce5f6095d0fed3d9978990122f |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: Make the use of PIDR to mark TLB entries controllable Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
mu-context.c
|
492e675116003b99dfcf0fa70084027e86bc0161 |
27-Oct-2010 |
David Howells <dhowells@redhat.com> |
MN10300: Rename __flush_tlb*() to local_flush_tlb*() Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <dhowells@redhat.com>
nit.c
mu-context.c
gtable.c
|
8f19e3daf3fffee9e18a8812067a6a4b538ae6c8 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: AM34 erratum requires MMUCTR read and write on exception entry An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
lb-mn10300.S
|
8be062892365b09f41d64cda7fa63d306e95e0c9 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: Cache: Implement SMP global cache flushing Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
akefile
ache-flush-icache.c
ache-inv-icache.c
ache-smp-flush.c
ache-smp-inv.c
ache-smp.c
ache-smp.h
ache.c
|
b478491f2628114b2eae76587f22ce3789b66012 |
27-Oct-2010 |
David Howells <dhowells@redhat.com> |
MN10300: Allow some cacheflushes to be avoided if cache snooping is available The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
akefile
ache-flush-icache.c
ache-inv-icache.c
ache.c
|
9731d23710736b96786d68c2e63148ff3f22e6eb |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: AM34: Add cacheflushing by using the AM34 purge registers The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
akefile
ache-flush-by-reg.S
ache-inv-by-reg.S
|
0bd3eb6ca772775da6125ea5b044d4257473d18d |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: SMP: Differentiate local cache flushing Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
ache-flush-by-tag.S
ache-inv-by-tag.S
|
9b287bf9924cedaf1accd7293db3627bef7c46e3 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: Cacheflush functions should take unsigned long addresses The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
ache-flush-by-tag.S
|
518d4bb7464dd3c04aeb23874dc360b54058c01e |
27-Oct-2010 |
David Howells <dhowells@redhat.com> |
MN10300: AM34: The current cacheflush routines operate by controlling tag regs The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
akefile
ache-flush-by-tag.S
ache-flush-mn10300.S
ache-inv-by-tag.S
ache-mn10300.S
|
344af921e6f23ea82487d76918d2643fcc88c311 |
27-Oct-2010 |
David Howells <dhowells@redhat.com> |
MN10300: Provide a MN10300_CACHE_ENABLED config option Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
|
0bc42d7fcb0acaab4202db97ff2de475424bf9b4 |
27-Oct-2010 |
David Howells <dhowells@redhat.com> |
MN10300: Cache: Split cache bits out of arch Kconfig Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <dhowells@redhat.com>
config.cache
|
86c0f935c1eee1d778b43895f80c9d27a896dfd9 |
27-Oct-2010 |
Akira Takeuchi <takeuchi.akr@jp.panasonic.com> |
MN10300: Remove monitor/JTAG functions Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
ault.c
|
292aa141277b142148d15bf28104f8890616e291 |
27-Oct-2010 |
Stoyan Gaydarov <stoyboyker@gmail.com> |
MN10300: BUG to BUG_ON changes Signed-off-by: Stoyan Gaydarov <stoyboyker@gmail.com> Signed-off-by: David Howells <dhowells@redhat.com>
nit.c
isalignment.c
|
57cf4f78c6266d5a6e5de5485065d4015b84bb30 |
01-Oct-2010 |
David Howells <dhowells@redhat.com> |
MN10300: Fix flush_icache_range() flush_icache_range() is given virtual addresses to describe the region. It deals with these by attempting to translate them through the current set of page tables. This is fine for userspace memory and vmalloc()'d areas as they are governed by page tables. However, since the regions above 0x80000000 aren't translated through the page tables by the MMU, the kernel doesn't bother to set up page tables for them (see paging_init()). This means flush_icache_range() as it stands cannot be used to flush regions of the VM area between 0x80000000 and 0x9fffffff where the kernel resides if the data cache is operating in WriteBack mode. To fix this, make flush_icache_range() first check for addresses in the upper half of VM space and deal with them appropriately, before dealing with any range in the page table mapped area. Ordinarily, this is not a problem, but it has the capacity to make kprobes and kgdb malfunction. It should not affect gdbstub, signal frame setup or module loading as gdb has its own flush functions, and the others take place in the page table mapped area only. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ache.c
|
62bdb288bf464862a2801b2e53aadc6c4d100fab |
29-Sep-2010 |
David Howells <dhowells@redhat.com> |
MN10300: Handle missing sys_cacheflush() when caching disabled When caching is disabled on the MN10300 arch, the sys_cacheflush() function is removed by conditional stuff in the makefiles, but is still referred to by the syscall table. Provide a null version that just returns 0 when caching is disabled (or -EINVAL if the arguments are silly). Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
akefile
ache-disabled.c
|
6e0c64f4ddf4a76a04108c1e24132d5d7dea8872 |
23-Aug-2010 |
Julia Lawall <julia@diku.dk> |
arch/mn10300/mm: eliminate NULL dereference dev_name always dereferences its argument, so it should not be called if the argument is NULL. The function indeed later tests the argument for being NULL. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression dev,E; @@ *dev_name(dev) ... when != dev = E ( *dev == NULL | *dev != NULL ) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ma-alloc.c
|
c421b08ef52f38049c6f591c5d260a97af7b0000 |
04-Jun-2010 |
Nick Piggin <npiggin@suse.de> |
mn10300: invoke oom-killer from page fault As explained in commit 1c0fe6e3bd ("mm: invoke oom-killer from page fault") , we want to call the architecture independent oom killer when getting an unexplained OOM from handle_mm_fault, rather than simply killing current. Signed-off-by: Nick Piggin <npiggin@suse.de> Acked-by: David Rientjes <rientjes@google.com> Acked-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ault.c
|
5a0e3ad6af8660be21ca98a971cd00f331318c05 |
24-Mar-2010 |
Tejun Heo <tj@kernel.org> |
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
ma-alloc.c
nit.c
gtable.c
|
4b3073e1c53a256275f1079c0fbfbe85883d9275 |
18-Dec-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
mu-context.c
|
012c79bad50469d964fda126102080d4b93a5946 |
08-Jan-2010 |
David Howells <dhowells@redhat.com> |
mn10300: make the ASB2305's PCnet32 NIC work by using the PCI bridge's SRAM Access to the ASB2305's PCnet32 NIC doesn't work correctly because when the NIC attempts to update the ring buffer flags by DMA, the change to RAM crops up about 17uS after the interrupt line is asserted. This is almost certainly due to a bug in the PCI bridge FPGA on that board. We can get around this by making dma_alloc_coherent() put the ring buffer in the SRAM attached to the PCI bridge rather than in the SDRAM. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ma-alloc.c
|
d6bb7a1ad326f56f0793353c59348554f84b513c |
08-Jan-2010 |
Mark Salter <msalter@redhat.com> |
mn10300: add cc clobbers to asm statements gcc 4.2.1 for MN10300 is more agressive than the older gcc in reordering/moving other insns between an insn that sets flags and an insn that uses those flags. This leads to trouble with asm statements which are missing an explicit "cc" clobber. This patch adds the explicit "cc" clobber to asm statements which do indeed clobber the condition flags. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
4b529401c5089cf33f7165607cbc2fde43357bfb |
08-Jan-2010 |
Andreas Fenkart <andreas.fenkart@streamunlimited.com> |
mm: make totalhigh_pages unsigned long Makes it consistent with the extern declaration, used when CONFIG_HIGHMEM is set Removes redundant casts in printout messages Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: Lennox Wu <lennox.wu@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
nit.c
|
cc013a88906bad9d2832d6316de1c7dbc1c2a794 |
22-Sep-2009 |
Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> |
arches: drop superfluous casts in nr_free_pages() callers Commit 96177299416dbccb73b54e6b344260154a445375 ("Drop free_pages()") modified nr_free_pages() to return 'unsigned long' instead of 'unsigned int'. This made the casts to 'unsigned long' in most callers superfluous, so remove them. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Reviewed-by: Christoph Lameter <cl@linux-foundation.org> Acked-by: Ingo Molnar <mingo@elte.hu> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Kyle McMartin <kyle@mcmartin.ca> Acked-by: WANG Cong <xiyou.wangcong@gmail.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Mikael Starvik <starvik@axis.com> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Chris Zankel <zankel@tensilica.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
nit.c
|
405f55712dfe464b3240d7816cc4fe4174831be2 |
11-Jul-2009 |
Alexey Dobriyan <adobriyan@gmail.com> |
headers: smp_lock.h redux * Remove smp_lock.h from files which don't need it (including some headers!) * Add smp_lock.h to files which do need it * Make smp_lock.h include conditional in hardirq.h It's needed only for one kernel_locked() usage which is under CONFIG_PREEMPT This will make hardirq.h inclusion cheaper for every PREEMPT=n config (which includes allmodconfig/allyesconfig, BTW) Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ault.c
isalignment.c
|
d06063cc221fdefcab86589e79ddfdb7c0e14b63 |
10-Apr-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
Move FAULT_FLAG_xyz into handle_mm_fault() callers This allows the callers to now pass down the full set of FAULT_FLAG_xyz flags to handle_mm_fault(). All callers have been (mechanically) converted to the new calling convention, there's almost certainly room for architectures to clean up their code and then add FAULT_FLAG_RETRY when that support is added. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ault.c
|
fd4f683d045e053abb093f80d81afce30ceadad2 |
11-Jun-2009 |
David Howells <dhowells@redhat.com> |
MN10300: Don't set the dirty bit in the DTLB entries in the TLB-miss handler Remove the special handling for the Data TLB entry dirty bit in the TLB-miss handler. As the code stands, all that it does is to cause us to take a second data address exception to set the dirty bit. Instead, we can just let pte_mkdirty() set the bit. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
lb-mn10300.S
|
58a47481b6ecb6dd05ab4a788e1f2ae3c7c46f57 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Don't do misalignment handling for userspace Don't do misalignment handling for userspace misalignment faults: just generate an appropriate SIGBUS instead. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
bd9384a9fdd6c15da6b01b2844c3471d07a45d64 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Don't handle misaligned loading and storing of SP Don't handle the misaligned loading and storing of the SP register as in C code that's most certainly a compiler bug. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
d3bd462865421dd8be310fac2d2f6da6069f9679 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Handle misaligned SP-based operands Support misalignment handling for instructions that have kernel SP-based address operands, including fixing those that include IMM8 or IMM16 displacements. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
852c15b7362cf34e0d7949abefbfeeb0845d93b4 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Fix misaligned index-register addressing handling Fix misalignment handling for an address calculated from the sum of two registers. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
6d615c78fb92fbd80e52ba7acb2d4c4d503006c3 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Handle misaligned postinc-with-imm addressing mode correctly Correctly handle misalignment in MOV instructions with postinc-with-immediate addressing mode operands. In these, the immediate value is the increment to be applied the address register, not the displacement to the address. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
ddb6d05cbaea76eddbee52585152ab801a8aedc7 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Perform misalignment fixups of MOV_Lcc Perform misalignment fixups of the MOV_Lcc instructions (move postinc memory to register and conditionally loop). Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
aefefbbec1ad25bafa97a7a1db25313ce26563e2 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Allow misalignment fixup in interrupt handling Allow misalignment fixup in interrupt handling in the MN10300 arch. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
f911c685d65ea1855eb3f95b8eaf871e5d9342fa |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Fix register-postinc addressing misalignment handling Fix misalignment handling of operands with register postincrement addressing. The flag to indicate that postincrement is required should not be interpreted as an specification of a value to be added to the address. Also add BUGs to catch unimplemented parameter markings in the opcodes table. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
b308bf3be1f75207c307eea9ada90e0b76194911 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Extract the displacement from an insn correctly in misalignment fixup Extract the displacement from an MN10300 instruction correctly in the misalignment fixup handler. The code should extract the displacement in LSB order, not MSB order. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
ee6e740cf7e5605b353af539eb9a6e17948747b6 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Add further misalignment fixups Add further misalignment fixup support to the MN10300 arch, notably for ABS32 and SP+disp addressing. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
9f55588968095306d52bd30564666d4fadce5e39 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Add built-in testing for misalignment handler Add configurable built-in testing for the MN10300 misalignment handler. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
31ea24bba77a16d3220b0822838785cbafb78175 |
12-Nov-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Clean up the misalignment handler a little Clean up the MN10300 misalignment handler a little by: (1) Use ilog2() rather than doing implementing log2() locally. (2) Make format_tbl[] const and static. (3) Making the debugging prints more consistent. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
isalignment.c
|
d1c6d2e547148c5aa0c0a4ff6aac82f7c6da1d8b |
11-Sep-2008 |
David Howells <dhowells@redhat.com> |
MN10300: Change the fault handler to check in_atomic() not in_interrupt() Change the MN10300 fault handler to make it check in_atomic() rather than in_interrupt() as commit 6edaf68a87d17570790fd55f0c451a29ec1d6703 did for other architectures: Author: Peter Zijlstra <a.p.zijlstra@chello.nl> Date: Wed Dec 6 20:32:18 2006 -0800 [PATCH] mm: arch do_page_fault() vs in_atomic() In light of the recent pagefault and filemap_copy_from_user work I've gone through all the arch pagefault handlers to make sure the inc_preempt_count() 'feature' works as expected. Several sections of code (including the new filemap_copy_from_user) rely on the fact that faults do not take locks under increased preempt count. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ault.c
|
4984d2d88805609e7702e8ee72b5e148c992ae7b |
26-Jul-2008 |
Johannes Weiner <hannes@saeurebad.de> |
mn10300: use generic show_mem() Remove arch-specific show_mem() in favor of the generic version. This also removes the following redundant information display: - free pages, printed by show_free_areas() - pages in swapcache, printed by show_swap_cache_info() where show_mem() calls show_free_areas(), which calls show_swap_cache_info(). Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Acked-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
gtable.c
|
3560e249abda6bee41a07a7bf0383a6e193e2839 |
24-Jul-2008 |
Johannes Weiner <hannes@saeurebad.de> |
bootmem: replace node_boot_start in struct bootmem_data Almost all users of this field need a PFN instead of a physical address, so replace node_boot_start with node_min_pfn. [Lee.Schermerhorn@hp.com: fix spurious BUG_ON() in mark_bootmem()] Signed-off-by: Johannes Weiner <hannes@saeureba.de> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Lee Schermerhorn <lee.schermerhorn@hp.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
nit.c
|
b920de1b77b72ca9432ac3f97edb26541e65e5dd |
08-Feb-2008 |
David Howells <dhowells@redhat.com> |
mn10300: add the MN10300/AM33 architecture to the kernel Add architecture support for the MN10300/AM33 CPUs produced by MEI to the kernel. This patch also adds board support for the ASB2303 with the ASB2308 daughter board, and the ASB2305. The only processor supported is the MN103E010, which is an AM33v2 core plus on-chip devices. [akpm@linux-foundation.org: nuke cvs control strings] Signed-off-by: Masakazu Urade <urade.masakazu@jp.panasonic.com> Signed-off-by: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
akefile
ache-flush-mn10300.S
ache-mn10300.S
ache.c
ma-alloc.c
xtable.c
ault.c
nit.c
isalignment.c
mu-context.c
gtable.c
lb-mn10300.S
|