| 7c8fb0411766849a332575673d0cc69ea571f031 |
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23-Jan-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
[CPUFREQ] s3c64xx: Fix mis-cherry pick of VDDINT
We don't have any of the other code for VDDINT, including the variable
declaration, so don't try to get it as we can't build.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Dave Jones <davej@redhat.com>
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| a6a434124457fe64bb3980ceb2170505207db6e5 |
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05-Dec-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
[CPUFREQ] s3c64xx: Use pr_fmt() for consistent log messages
They're already consistent but it saves remembering to do so.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Dave Jones <davej@redhat.com>
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| a6ee87790b708dc4cdd3643104417793f0d985ec |
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29-Jul-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
cpufreq: Fix build of s3c64xx cpufreq driver for header change
The header change has removed an implicit include of module.h, breaking
the build due to the use of THIS_MODULE. Fix that.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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| ef993ef8dcd4f3e4d058400c5bd2f7c547344e74 |
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29-Jun-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
[CPUFREQ] S3C6410: Add some lower frequencies for 800MHz base clock operation
By extension from the 667MHz based clocks currently supported add 100MHz
and 200MHz operating points. Due to a lack of documentation these have not
been confirmed as supported but by extension from the existing frequencies
they should be OK, and I've given them quite a bit of runtime testing.
The major risk is synchronization with the non-ARM clocks but as we
can't currently scale the ARM PLL the risk should be relatively low.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Dave Jones <davej@redhat.com>
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| fb3b1fefaaccdbdc716db0963ba41fb6b4221e60 |
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22-Jun-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
[CPUFREQ] S3C64xx: Notify transition complete as soon as frequency changed
The CPUFREQ_POSTCHANGE notification is used to update things that depend on
the system clock rates. Since this may include the interfaces used to talk
to the regulators do the notification before we try to update regulators
to reflect lowered system clock rate.
The voltage scaling is just a power optimisation and may not happen at all
so there's no concern about it not having completed.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Dave Jones <davej@redhat.com>
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| c6e2d68558b612fdfdb0d7ddcb51ad4578b81eba |
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08-Jun-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
[CPUFREQ] S3C6410: Support 800MHz operation in cpufreq
At least some newer S3C6410 silicon supports operation up to 800MHz rather
than just 667MHz. Unfortunately I don't have access to any of documentation
of this other than some running systems, add a new cpufreq table entry for
this based on the behaviour of those systems.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Dave Jones <davej@redhat.com>
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| 15964d388528c1dbb672027c8003fe7e81630a35 |
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07-Jun-2011 |
Kukjin Kim <kgene.kim@samsung.com> |
[CPUFREQ] Move compile for S3C64XX cpufreq to /drivers/cpufreq
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Dave Jones <davej@redhat.com>
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