| 185ecb5f4fd43911c35956d4cc7d94a1da30417f |
|
08-Mar-2012 |
Alexandre Bounine <alexandre.bounine@idt.com> |
dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclic
Add context parameter to device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to allow passing client/target specific information associated
with the data transfer.
Modify all affected DMA engine drivers.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| d3ee98cdcd6198ea1cf75c603178acc8a805b69b |
|
06-Mar-2012 |
Russell King - ARM Linux <linux@arm.linux.org.uk> |
dmaengine: consolidate initialization of cookies
Provide a common function to initialize a channels cookie values.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 96a2af41c78b1fbb1f567a3486bdc63f7b31c5fd |
|
06-Mar-2012 |
Russell King - ARM Linux <linux@arm.linux.org.uk> |
dmaengine: consolidate tx_status functions
Now that we have the completed cookie in the dma_chan structure, we
can consolidate the tx_status functions by providing a function to set
the txstate structure and returning the DMA status. We also provide
a separate helper to set the residue for cookies which are still in
progress.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| f7fbce07c6ce26a25b4e0cb5f241c361fde87901 |
|
06-Mar-2012 |
Russell King - ARM Linux <linux@arm.linux.org.uk> |
dmaengine: provide a common function for completing a dma descriptor
Provide a common function to do the cookie mechanics for completing
a DMA descriptor.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 884485e1f12dcd39390f042e772cdbefc9ebb750 |
|
06-Mar-2012 |
Russell King - ARM Linux <linux@arm.linux.org.uk> |
dmaengine: consolidate assignment of DMA cookies
Everyone deals with assigning DMA cookies in the same way (it's part of
the API so they should be), so lets consolidate the common code into a
helper function to avoid this duplication.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| d2ebfb335b0426deb1a4fb14e4e926d81ecd8235 |
|
06-Mar-2012 |
Russell King - ARM Linux <linux@arm.linux.org.uk> |
dmaengine: add private header file
Add a local private header file to contain definitions and declarations
which should only be used by DMA engine drivers.
We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
multiple inclusion.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 4d4e58de32a192fea65ab84509d17d199bd291c8 |
|
06-Mar-2012 |
Russell King - ARM Linux <linux@arm.linux.org.uk> |
dmaengine: move last completed cookie into generic dma_chan structure
Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures. This is pointless, and
forces driver specific code. Move this out into the common dma_chan
structure.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 327e6970258618da810f72e86cf2a8b803927e14 |
|
01-Feb-2012 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Add support for DMA_SLAVE_CONFIG
This patch adds support for DMA_SLAVE_CONFIG in dwc DMAC controller. Fields in
struct dw_dma_slave for passing similar data are preserved in this patch untill
all existing users are fixed.
That will be handled later in this patchset.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 6bc711f6bd9dd393e1f9bbae354906affcd02aa5 |
|
01-Feb-2012 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Add 64 bit access width support for slave xfers on mem side
64 bit transfers are possible on both sides in slave transfers (memory as well
as peripherals). This patch adds support for it memory side 64 bit transfers.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| ff7b05f29fd4db810021d905e2dad95ab4fe2984 |
|
01-Feb-2012 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Don't handle block interrupts
Block interrupts give interrupt on completion of every LLI, which is actually
too much interrupts. This is just not required for current functioning of
dw_dmac.
So, just don't handle them at all.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 6c618c9de5f2b4b43c30c6203869620bec6ed929 |
|
01-Feb-2012 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Use dev_get_platdata() instead of accessing dev directly
Use already defined function dev_get_platdata() instead of accessing
pdev->dev.data.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| e8d9f875c9b02bb56ba3bb44834ae81ba0e8efbc |
|
01-Feb-2012 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Don't use magic number for total number of channels
Total number of channels is passed in pdata->nr_channels variable, thus we must
not use magic number '7' for total number of channels.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 7414a1b8b2b99093d6a271a1220557e87dc1ae94 |
|
01-Feb-2012 |
Rajeev KUMAR <rajeev-dlh.kumar@st.com> |
dmaengine/dw_dmac: Hibernation support in dw_dmac
The suspend and resume implementation is through dev_pm_ops in dmac. So
in order to support hibernation, freeze, thaw, restore and poweroff
features are required.
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 61e183f8306934a9f66557f69f1f0f56f18dca06 |
|
17-Nov-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume
In S2R all DMA registers are reset by hardware and thus they are required to be
reprogrammed. The channels which aren't reprogrammed are channel configuration
and interrupt enable registers, which are currently programmed at chan_alloc
time.
This patch creates another routine to initialize a channel. It will try to
initialize channel on every dwc_dostart() call. If channel is already
initialised then it simply returns, otherwise it configures registers.
This routine will also initialize registers on wakeup from S2R, as we mark
channels as uninitialized on suspend.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| db8196df4bb6f117caa163aa73b0f16fd62290bd |
|
13-Oct-2011 |
Vinod Koul <vinod.koul@linux.intel.com> |
dmaengine: move drivers to dma_transfer_direction
fixup usage of dma direction by introducing dma_transfer_direction,
this patch moves dma/drivers/* to use new enum
Cc: Jassi Brar <jaswinder.singh@linaro.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Mika Westerberg <mika.westerberg@iki.fi>
Cc: H Hartley Sweeten <hartleys@visionengravers.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Zhang Wei <zw@zh-kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Yong Wang <yong.y.wang@intel.com>
Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
Cc: Boojin Kim <boojin.kim@samsung.com>
Cc: Barry Song <Baohua.Song@csr.com>
Acked-by: Mika Westerberg <mika.westerberg@iki.fi>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
/drivers/dma/dw_dmac.c
|
| 463894705e4089d0ff69e7d877312d496ac70e5b |
|
15-Sep-2011 |
Barry Song <Baohua.Song@csr.com> |
dmaengine: delete redundant chan_id and chancnt initialization in dma drivers
dma_async_device_register will re-init chan_id and chancnt,
so whatever chan_id and chancnt are set in drivers, they will
be re-written by dma_async_device_register.
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Piotr Ziecik <kosmo@semihalf.com>
Cc: Yong Wang <yong.y.wang@intel.com>
Cc: Jaswinder Singh <jassi.brar@samsung.com>
Cc: Pelagicore AB <info@pelagicore.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 4cb865deec59ef31d966622d1ec87411ae32dfab |
|
28-May-2011 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (33 commits)
x86: poll waiting for I/OAT DMA channel status
maintainers: add dma engine tree details
dmaengine: add TODO items for future work on dma drivers
dmaengine: Add API documentation for slave dma usage
dmaengine/dw_dmac: Update maintainer-ship
dmaengine: move link order
dmaengine/dw_dmac: implement pause and resume in dwc_control
dmaengine/dw_dmac: Replace spin_lock* with irqsave variants and enable submission from callback
dmaengine/dw_dmac: Divide one sg to many desc, if sg len is greater than DWC_MAX_COUNT
dmaengine/dw_dmac: set residue as total len in dwc_tx_status if status is !DMA_SUCCESS
dmaengine/dw_dmac: don't call callback routine in case dmaengine_terminate_all() is called
dmaengine: at_hdmac: pause: no need to wait for FIFO empty
pch_dma: modify pci device table definition
pch_dma: Support new device ML7223 IOH
pch_dma: Support I2S for ML7213 IOH
pch_dma: Fix DMA setting issue
pch_dma: modify for checkpatch
pch_dma: fix dma direction issue for ML7213 IOH video-in
dmaengine: at_hdmac: use descriptor chaining help function
dmaengine: at_hdmac: implement pause and resume in atc_control
...
Fix up trivial conflict in drivers/dma/dw_dmac.c
|
| aecb7b64dd9e2512c7a4c7e61dd781415d3dac5a |
|
24-May-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Update maintainer-ship
Nobody is currently maintaining dw_dmac. We are using dw_dmac for SPEAr13xx and
are currently maintaining it. After discussing with Vinod, sending this patch to
update maintainer-ship of dw_dmac.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Havard Skinnemoen <hskinnemoen@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| e05503ef1186ad33dfe56794407891eb1dd93ef6 |
|
18-May-2011 |
Jean Delvare <khali@linux-fr.org> |
Haavard Skinnemoen has left Atmel
Haavard's e-mail address at Atmel is no longer valid.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Acked-by: Havard Skinnemoen <hskinnemoen@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
/drivers/dma/dw_dmac.c
|
| a7c57cf7d4327c41510f8cbf45b1b970e02c34f8 |
|
19-Apr-2011 |
Linus Walleij <linus.walleij@linaro.org> |
dmaengine/dw_dmac: implement pause and resume in dwc_control
Some peripherals like amba-pl011 needs pause to be implemented in DMA controller
drivers. This also returns correct status from dwc_tx_status() in case chan is
paused.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 69cea5a00d3135677939fce1fefe54ed522055a0 |
|
15-Apr-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Replace spin_lock* with irqsave variants and enable submission from callback
dmaengine routines can be called from interrupt context and with interrupts
disabled. Whereas spin_unlock_bh can't be called from such contexts. So this
patch converts all spin_*_bh routines to irqsave variants.
Also, spin_lock() used in tasklet is converted to irqsave variants, as tasklet
can be interrupted, and dma requests from such interruptions may also call
spin_lock.
Now, submission from callbacks are permitted as per dmaengine framework. So we
shouldn't hold any locks while calling callbacks. As locks were taken by parent
routines, so releasing them before calling callbacks doesn't look clean enough.
So, locks are taken inside all routine now, whereever they are required. And
dwc_descriptor_complete is always called without taking locks.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 69dc14b51c1aad9d82afd8f96bf4e4835089bffc |
|
18-Apr-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: Divide one sg to many desc, if sg len is greater than DWC_MAX_COUNT
If len passed in sg for slave_sg transfers is greater than DWC_MAX_COUNT, then
driver programmes controller incorrectly. This patch adds code to handle this
situation by allocation more than one desc for same sg.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| abf53902dcc6d44d2e06b09817fa67857aa686fe |
|
15-Apr-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: set residue as total len in dwc_tx_status if status is !DMA_SUCCESS
If transfer status is !=DMA_SUCCESS, return total transfer len as residue,
instead of zero.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 5fedefb87bd0a64281d28edd295f29e3b989d78c |
|
15-Apr-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac: don't call callback routine in case dmaengine_terminate_all() is called
If dmaengine_terminate_all() is called for dma channel, then it doesn't make
much sense to call registered callback routine. While in case of success or
failure it must be called.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 84adccfb8cd2a6b8237da6752668ba25cd90c20b |
|
24-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dmaengine/dw_dmac fix: dwc_scan_descriptors must compare first desc address also with llp
dwc_scan_descriptors scans all descriptors from active_list in case transfer is
not completed. It compares first_desc->lli.llp, and then all childrens of its
tx_list. But it doesn't compare its own address, i.e. first_desc->txd.phys, as
this is what we have initially programmed into the controller register. So this
causes dma to stop and finish a transfer, which was never started. And thus
fail.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| e51dc53b8c7fa2d9ac4ef8f317f5dfe07a79e65a |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Setting Default Burst length for transfers as 16.
This patch sets default Burst length for all transfer to 16. This will
enhance performance when user doesn't have any chan->private data.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| ee66509d7f354eecb45ac99f21ea6aa8650dea7e |
|
04-Mar-2011 |
Viresh KUMAR <viresh.kumar@st.com> |
dw_dmac: Allow src/dst msize & flow controller to be configured at runtime
Msize or Burst Size is peripheral dependent in case of prep_slave_sg and
cyclic_prep transfers, and in case of memcpy transfers it is platform dependent.
So msize configuration must come from platform data.
Also some peripherals (ex: JPEG), need to be flow controller for dma transfers,
so this information in case of slave_sg & cyclic_prep transfers must come from
platform data.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 93317e8e35b77633d589fe0e132291195757d785 |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Pass Channel Priority from platform_data
In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| b0c3130d69bda5cd91aa3b3f08e7878df49fde69 |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Pass Channel Allocation Order from platform_data
In SPEAr Platform channels 4-7 have more Fifo depth. So we must get better
channel first. This patch introduces concept of channel allocation order in
dw_dmac. If user doesn't pass anything or 0, than normal (ascending) channel
allocation will follow, else channels will be allocated in descending order.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| e518076ef8cb56adb558ff56ad5bfa0cd9f3abd9 |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finish
dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for
transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer
finishes. Thus descriptor once used is not usable again. This patch marks
descriptors with DMA_CRTL_ACK after dma xfer finishes
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 418e74070662e1ae7d9bb5202f773d35c9a7f05e |
|
04-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Change value of DWC_MAX_COUNT to 4095.
Every descriptor can transfer a maximum count of 4095 (12 bits, in control reg),
So we must have DWC_MAX_COUNT as 4095 instead of 2048.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| a02274564dd78f7edde3c9ff197ed44f2f8a5a81 |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Adding support for 64 bit access width for memcpy xfers
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 569432efa7975f5795efb8142134f5a098942381 |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lock
Lock must be taken before calling dwc_scan_descriptors, as this may
access/modify shared data and queues. dwc_tx_status wasn't taking lock before
calling this routine. This patch add code that takes lock before calling
dwc_scan_descriptors.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| f336e42f73d93b74fd21bf9176ee6c7ab8b195c5 |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in dwc_complete_all
dwc_complete_all and other routines was removing all descriptors from dwc->queue
and pushing them to dwc->active_list. Only one was required to be removed. Also
we are calling dwc_dostart, once list is fixed.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| cb689a706d17ef19a61735670ded60466dd015fa |
|
03-Mar-2011 |
Viresh Kumar <viresh.kumar@st.com> |
dw_dmac: Replace module_init() with subsys_initcall()
In some cases users of dw_dmac are initialized before dw_dmac, and if they try
to use dw_dmac, they simply fail. So its better we register init() routine
of driver using subsys_initcall() instead of module_init(), so that dma driver
is available at the earliest possible.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
/drivers/dma/dw_dmac.c
|
| 95ea759e9e116dade3e7386be2a3db76c90f4675 |
|
21-Jan-2011 |
Jamie Iles <jamie@jamieiles.com> |
dmaengine/dw_dmac: provide a mechanism to indicate private devices
Some platforms (e.g. Picochip PC3XX) have multiple DMA controllers
where some may be used for slave transfers and others for general
purpose memcpy type transfers. Add a .is_private boolean to the
platform data structure so that controllers can be marked as private
so that the DMA_PRIVATE capability will be set for that controller.
Signed-off-by: Jamie Iles <jamie.iles@picochip.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| f301c062dcdd113bc977ae1ebc8c12232f8531a9 |
|
21-Jan-2011 |
Jamie Iles <jamie@jamieiles.com> |
dmaengine/dw_dmac: allow src/dst masters to be configured at runtime
Some platforms have flexible mastering capabilities and this needs
to be selected at runtime. If the platform has specified private
data in the form of the dw_dma_slave then fetch the source and
destination masters from here. If this isn't present, default to
the previous of 0 and 1.
v2: cleanup whitespace
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Signed-off-by: Jamie Iles <jamie.iles@picochip.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 087809fce28f50098d9c3ef1a6865c722f23afd2 |
|
21-Jan-2011 |
Jamie Iles <jamie@jamieiles.com> |
dmaengine/dw_dmac: don't scan descriptors if no xfers in progress
Some hardware (picoChip picoXCell in particular) sometimes has
the block transfer complete bit being set for a channel after the
whole transfer has completed. If we don't have any transfers in the
active list then don't bother to scan the descriptors. This often
happens in normal operation and doesn't require the channel to be
reset.
v2: cleanup whitespace
Signed-off-by: Jamie Iles <jamie.iles@picochip.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 058276303dbc4ed089c1f7dad0871810b1f5ddf1 |
|
18-May-2010 |
Linus Walleij <linus.walleij@stericsson.com> |
DMAENGINE: extend the control command to include an arg
This adds an argument to the DMAengine control function, so that
we can later provide control commands that need some external data
passed in through an argument akin to the ioctl() operation
prototype.
[dan.j.williams@intel.com: fix up some missed conversions]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| bca3469205402d9fb14060d255d8786ae2256640 |
|
27-Mar-2010 |
Dan Williams <dan.j.williams@intel.com> |
dmaengine: provide helper for setting txstate
Simple conditional struct filler to cut out some duplicated code.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 0793448187643b50af89d36b08470baf45a3cab4 |
|
27-Mar-2010 |
Linus Walleij <linus.walleij@stericsson.com> |
DMAENGINE: generic channel status v2
Convert the device_is_tx_complete() operation on the
DMA engine to a generic device_tx_status()operation which
can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,
DMA_TX_PAUSED.
[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Maciej Sosnowski <maciej.sosnowski@intel.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Li Yang <leoli@freescale.com>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Magnus Damm <damm@opensource.se>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Joe Perches <joe@perches.com>
Cc: Roland Dreier <rdreier@cisco.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| c3635c78e500a52c9fcd55de381a72928d9e054d |
|
27-Mar-2010 |
Linus Walleij <linus.walleij@stericsson.com> |
DMAENGINE: generic slave control v2
Convert the device_terminate_all() operation on the
DMA engine to a generic device_control() operation
which can now optionally support also pausing and
resuming DMA on a certain channel. Implemented for the
COH 901 318 DMAC as an example.
[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Maciej Sosnowski <maciej.sosnowski@intel.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Li Yang <leoli@freescale.com>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Magnus Damm <damm@opensource.se>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Joe Perches <joe@perches.com>
Cc: Roland Dreier <rdreier@cisco.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 05a625486efc3209ae4d98e253dafa6ce0124385 |
|
30-Dec-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
drivers/dma: Correct use after free
drivers/dma: drop unnecesary memset
ioat2,3: put channel hardware in known state at init
async_tx: expand async raid6 test to cover ioatdma corner case
ioat3: fix p-disabled q-continuation
sh: fix DMA driver's descriptor chaining and cookie assignment
dma: at_hdmac: correct incompatible type for argument 1 of 'spin_lock_bh'
|
| 1e9d1b13efae7e0a2705611d47ae5f07e27015f0 |
|
19-Dec-2009 |
Julia Lawall <julia@diku.dk> |
drivers/dma: drop unnecesary memset
memset of 0 is not needed after kzalloc
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
expression x;
statement S;
@@
x = kzalloc(...);
if (x == NULL) S
... when != x
-memset(x,0,...);// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 471452104b8520337ae2fb48c4e61cd4896e025d |
|
15-Dec-2009 |
Alexey Dobriyan <adobriyan@gmail.com> |
const: constify remaining dev_pm_ops
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
/drivers/dma/dw_dmac.c
|
| 4b3df5668c8ebaebd8d66a5a94374be3e3b2ef0c |
|
23-Sep-2009 |
NeilBrown <neilb@suse.de> |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx into for-linus
|
| 657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 |
|
09-Sep-2009 |
Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
dmaengine: Move all map_sg/unmap_sg for slave channel to its client
Dan Williams wrote:
... DMA-slave clients request specific channels and know the hardware
details at a low level, so it should not be too high an expectation to
push dma mapping responsibility to the client.
Also this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for
dw_dmac driver.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c |
|
09-Sep-2009 |
Dan Williams <dan.j.williams@intel.com> |
dw_dmac: implement a private tx_list
Drop dw_dmac's use of tx_list from struct dma_async_tx_descriptor in
preparation for removal of this field.
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 4a256b5fc028e6dad0fd1b59745f743ee528c944 |
|
08-Jul-2009 |
Magnus Damm <damm@igel.co.jp> |
DMA: Rework dw_dmac suspend_late()/resume_early()
This patch reworks platform driver power management code
for dw_dmac from legacy late/early callbacks to dev_pm_ops.
The callbacks are converted for CONFIG_SUSPEND like this:
suspend_late() -> suspend_noirq()
resume_early() -> resume_noirq()
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
/drivers/dma/dw_dmac.c
|
| 133e2a3164771454aa326859c2b293687189b553 |
|
03-Apr-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup
dw_dmac: add cyclic API to DW DMA driver
dmaengine: Add privatecnt to revert DMA_PRIVATE property
dmatest: add dma interrupts and callbacks
dmatest: add xor test
dmaengine: allow dma support for async_tx to be toggled
async_tx: provide __async_inline for HAS_DMA=n archs
dmaengine: kill some unused headers
dmaengine: initialize tx_list in dma_async_tx_descriptor_init
dma: i.MX31 IPU DMA robustness improvements
dma: improve section assignment in i.MX31 IPU DMA driver
dma: ipu_idmac driver cosmetic clean-up
dmaengine: fail device registration if channel registration fails
|
| d9de451989a88a2003ca06e524aca4665c0c7f06 |
|
01-Apr-2009 |
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> |
dw_dmac: add cyclic API to DW DMA driver
This patch adds a cyclic DMA interface to the DW DMA driver. This is
very useful if you want to use the DMA controller in combination with a
sound device which uses cyclic buffers.
Using a DMA channel for cyclic DMA will disable the possibility to use
it as a normal DMA engine until the user calls the cyclic free function
on the DMA channel. Also a cyclic DMA list can not be prepared if the
channel is already active.
Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| ccccce229c633a92c42cd1a40c0738d7b0d12644 |
|
25-Mar-2009 |
Dan Williams <dan.j.williams@intel.com> |
dmaengine: initialize tx_list in dma_async_tx_descriptor_init
Centralize this common initialization (and one case where ipu_idmac is
duplicating ->chan initialization).
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| dfbc90196dfb9a814e7f2e1f4c47aa425452d313 |
|
25-Mar-2009 |
Kay Sievers <kay.sievers@vrfy.org> |
dma: struct device - replace bus_id with dev_name(), dev_set_name()
Cc: Dan Williams <dan.j.williams@intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Kay Sievers <kay.sievers@vrfy.org>
/drivers/dma/dw_dmac.c
|
| 287d859222e0adbc67666a6154aaf42d7d5bbb54 |
|
18-Feb-2009 |
Dan Williams <dan.j.williams@intel.com> |
atmel-mci: fix initialization of dma slave data
The conversion of atmel-mci to dma_request_channel missed the
initialization of the channel dma_slave information. The filter_fn passed
to dma_request_channel is responsible for initializing the channel's
private data. This implementation has the additional benefit of enabling
a generic client-channel data passing mechanism.
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
/drivers/dma/dw_dmac.c
|
| 41d5e59c1299f27983977bcfe3b360600996051c |
|
06-Jan-2009 |
Dan Williams <dan.j.williams@intel.com> |
dmaengine: add a release for dma class devices and dependent infrastructure
Resolves:
WARNING: at drivers/base/core.c:122 device_release+0x4d/0x52()
Device 'dma0chan0' does not have a release() function, it is broken and must be fixed.
The dma_chan_dev object is introduced to gear-match sysfs kobject and
dmaengine channel lifetimes. When a channel is removed access to the
sysfs entries return -ENODEV until the kobject can be released.
The bulk of the change is updates to existing code to handle the extra
layer of indirection between a dma_chan and its struct device.
Reported-by: Alexander Beregalov <a.beregalov@gmail.com>
Acked-by: Stephen Hemminger <shemminger@vyatta.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| aa1e6f1a385eb2b04171ec841f3b760091e4a8ee |
|
06-Jan-2009 |
Dan Williams <dan.j.williams@intel.com> |
dmaengine: kill struct dma_client and supporting infrastructure
All users have been converted to either the general-purpose allocator,
dma_find_channel, or dma_request_channel.
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 74465b4ff9ac1da503025c0a0042e023bfa6505c |
|
06-Jan-2009 |
Dan Williams <dan.j.williams@intel.com> |
atmel-mci: convert to dma_request_channel and down-level dma_slave
dma_request_channel provides an exclusive channel, so we no longer need to
pass slave data through dmaengine.
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1 |
|
06-Jan-2009 |
Dan Williams <dan.j.williams@intel.com> |
dmaengine: up-level reference counting to the module level
Simply, if a client wants any dmaengine channel then prevent all dmaengine
modules from being removed. Once the clients are done re-enable module
removal.
Why?, beyond reducing complication:
1/ Tracking reference counts per-transaction in an efficient manner, as
is currently done, requires a complicated scheme to avoid cache-line
bouncing effects.
2/ Per-transaction ref-counting gives the false impression that a
dma-driver can be gracefully removed ahead of its user (net, md, or
dma-slave)
3/ None of the in-tree dma-drivers talk to hot pluggable hardware, but
if such an engine were built one day we still would not need to notify
clients of remove events. The driver can simply return NULL to a
->prep() request, something that is much easier for a client to handle.
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|
| 7fe7b2f4ec14d6517078c5bc32b04301b468041c |
|
04-Oct-2008 |
Haavard Skinnemoen <haavard.skinnemoen@atmel.com> |
dw_dmac: fix copy/paste bug in tasklet
The tasklet checks RAW.BLOCK twice, and does not check RAW.XFER. This is
obviously wrong, and could theoretically cause the driver to hang.
Reported-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
/drivers/dma/dw_dmac.c
|
| 3bfb1d20b547a5071d01344581eac5846ea84491 |
|
08-Jul-2008 |
Haavard Skinnemoen <haavard.skinnemoen@atmel.com> |
dmaengine: Driver for the Synopsys DesignWare DMA controller
This adds a driver for the Synopsys DesignWare DMA controller (aka
DMACA on AVR32 systems.) This DMA controller can be found integrated
on the AT32AP7000 chip and is primarily meant for peripheral DMA
transfer, but can also be used for memory-to-memory transfers.
This patch is based on a driver from David Brownell which was based on
an older version of the DMA Engine framework. It also implements the
proposed extensions to the DMA Engine API for slave DMA operations.
The dmatest client shows no problems, but there may still be room for
improvement performance-wise. DMA slave transfer performance is
definitely "good enough"; reading 100 MiB from an SD card running at ~20
MHz yields ~7.2 MiB/s average transfer rate.
Full documentation for this controller can be found in the Synopsys
DW AHB DMAC Databook:
http://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf
The controller has lots of implementation options, so it's usually a
good idea to check the data sheet of the chip it's intergrated on as
well. The AT32AP7000 data sheet can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Changes since v4:
* Use client_count instead of dma_chan_is_in_use()
* Add missing include
* Unmap buffers unless client told us not to
Changes since v3:
* Update to latest DMA engine and DMA slave APIs
* Embed the hw descriptor into the sw descriptor
* Clean up and update MODULE_DESCRIPTION, copyright date, etc.
Changes since v2:
* Dequeue all pending transfers in terminate_all()
* Rename dw_dmac.h -> dw_dmac_regs.h
* Define and use controller-specific dma_slave data
* Fix up a few outdated comments
* Define hardware registers as structs (doesn't generate better
code, unfortunately, but it looks nicer.)
* Get number of channels from platform_data instead of hardcoding it
based on CONFIG_WHATEVER_CPU.
* Give slave clients exclusive access to the channel
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>,
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
/drivers/dma/dw_dmac.c
|