| 650dc07ec3b0eba8ff21da706d2b1876ada59fc3 |
|
02-Apr-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: disable ppgtt on snb when dmar is enabled
Totally unexpected that this regressed. Luckily it sounds like we just
need to have dmar disable on the igfx, not the entire system. At least
that's what a few days of testing between Tony Vroon and me indicates.
Reported-by: Tony Vroon <tony@linx.net>
Cc: Tony Vroon <tony@linx.net>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43024
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 83b7f9ac9126f0532ca34c14e4f0582c565c6b0d |
|
23-Mar-2012 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
drm/i915: allow to select rc6 modes via kernel parameter
This allows to select which rc6 modes are to be used via kernel parameter,
via a bitmask parameter. E.g.:
- to enable rc6, i915_enable_rc6=1
- to enable rc6 and deep rc6, i915_enable_rc6=3
- to enable rc6 and deepest rc6, use i915_enable_rc6=5
- to enable rc6, deep and deepest rc6, use i915_enable_rc6=7
Please keep in mind that the deepest RC6 state really should NOT be used
by default, as it could potentially worsen the issues with deep RC6. So do
enable it only when you know what you are doing. However, having it around
could help solving possible future rc6-related issues and their debugging
on user machines.
Note that this changes behavior - previously, value of 1 would enable both
RC6 and deep RC6. Now it should only enable RC6 and deep/deepest RC6
stages must be enabled manually.
v2: address Chris Wilson comments and clean up the code.
References: https://bugs.freedesktop.org/show_bug.cgi?id=42579
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| f6f808c8e1c4a3b7e3e0a6cb81541ec615aeb5fd |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: i2c: unconditionally set up gpio fallback
This way we can simplify the setup and teardown a bit.
Because we don't actually allocate anything anymore for the force_bit
case, we can now convert that into a boolean.
Also and the functionality supported by the bit-banging together with
what gmbus can do, so that this doesn't randomly change any more.
v2: Chris Wilson noticed that I've mixed up && and & ...
v3: Clarify an if block as suggested by Eugeni Dodonov.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| c167a6fc6ed78a300c29181a6caf9ae1b9993289 |
|
28-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: merge gmbus and gpio i2c adpater into one
... and directly call the newly exported i2c bit-banging functions.
The code is still pretty convoluted because we only set up the gpio
i2c stuff when actually falling back, resulting in more complexity
than necessary. This will be fixed up in the next patch.
v2: Use exported i2c_bit_algo vtable instead of exported functions.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 36c785f051b21728775c9c4f2621d37d586553d0 |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: merge struct intel_gpio into struct intel_gmbus
When we set up the gpio fallback, we always have a 1:1 relationship
with an intel_gmbus. Exploit that to store all gpio related data in
there, too. This is a preparation step to merge the tw i2c adapters
controlling the same bus into one.
Just mundane code-munging in this patch.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| c2b9152f098e213dc5f2e8a4dbbfe090302c58ed |
|
14-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: add dev_priv to intel_gmbus
This way we can free up the bus->adaptor.algo_data pointer and make it
available for use with the bitbanging fallback algo.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5d1333fcce84e77ec865f6b09006401ed3f564b5 |
|
16-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: error_buffer->ring should be signed
gcc seems to get uber-anal recently about these things.
Clarification from Dan Carpenter:
"Sorry, I should have said that it's not a gcc warning, it's a smatch
thing. But also it's not uber-anal. It's the exact level of anality
which is required to make the == -1 test work. You can compare
unsigned int and longs to -1 and it works but for smaller types it
doesn't."
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| ee4f42b10bbc404579c2e6f446b24d898592753c |
|
15-Feb-2012 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record the position of the request upon error
So that we can tally the request against the command sequence in the
ringbuffer, or merely jump to the interesting locations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 52d39a21350531063bf8f4f704101bd371ea5d7d |
|
15-Feb-2012 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record the in-flight requests at the time of a hang
Being able to tally the list of outstanding requests with the sequence
of commands in the ringbuffer is often useful evidence with respect to
driver corruption.
Note that since this is the umpteenth per-ring data structure to be added
to the error state, I've coallesced the nearby loops (the ringbuffer and
batchbuffer) into a single structure along with the list of requests. A
later task would be to refactor the ring register state into the same
structure.
v2: Fix pretty printing of requests so that they are parsed correctly by
intel_error_decode and use the 0x%08x format for seqno for consistency
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| a71d8d94525e8fd855c0466fb586ae1cb008f3a2 |
|
15-Feb-2012 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record the tail at each request and use it to estimate the head
By recording the location of every request in the ringbuffer, we know
that in order to retire the request the GPU must have finished reading
it and so the GPU head is now beyond the tail of the request. We can
therefore provide a conservative estimate of where the GPU is reading
from in order to avoid having to read back the ring buffer registers
when polling for space upon starting a new write into the ringbuffer.
A secondary effect is that this allows us to convert
intel_ring_buffer_wait() to use i915_wait_request() and so consolidate
upon the single function to handle the complicated task of waiting upon
the GPU. A necessary precaution is that we need to make that wait
uninterruptible to match the existing conditions as all the callers of
intel_ring_begin() have not been audited to handle ERESTARTSYS
correctly.
By using a conservative estimate for the head, and always processing all
outstanding requests first, we prevent a race condition between using
the estimate and direct reads of I915_RING_HEAD which could result in
the value of the head going backwards, and the tail overflowing once
again. We are also careful to mark any request that we skip over in
order to free space in ring as consumed which provides a
self-consistency check.
Given sufficient abuse, such as a set of unthrottled GPU bound
cairo-traces, avoiding the use of I915_RING_HEAD gives a 10-20% boost on
Sandy Bridge (i5-2520m):
firefox-paintball 18927ms -> 15646ms: 1.21x speedup
firefox-fishtank 12563ms -> 11278ms: 1.11x speedup
which is a mild consolation for the performance those traces achieved from
exploiting the buggy autoreported head.
v2: Add a few more comments and make request->tail a conservative
estimate as suggested by Daniel Vetter.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: resolve conflicts with retirement defering and the lack of
the autoreport head removal (that will go in through -fixes).]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8a8ed1f5143b3df312e436ab15290e4a7ca6a559 |
|
13-Feb-2012 |
Yufeng Shen <miletus@chromium.org> |
drm/i915: Fix race condition in accessing GMBUS
GMBUS has several ports and each has it's own corresponding
I2C adpater. When multiple I2C adapters call gmbus_xfer() at
the same time there is a race condition in using the underlying
GMBUS controller. Fixing this by adding a mutex lock when calling
gmbus_xfer().
v2: Moved gmbus_mutex below intel_gmbus and added comments.
Rebased to drm-intel-next-queued.
Signed-off-by: Yufeng Shen <miletus@chromium.org>
[danvet: Shortened the gmbus_mutex comment a bit and add the patch
revision comment to the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| b1d7e4b41fd0f72ea8149056778db5d737739305 |
|
14-Feb-2012 |
Wu Fengguang <fengguang.wu@intel.com> |
drm/i915: add a "force-dvi" HDMI audio mode
When HDMI-DVI converter is used, it's not only necessary to turn off
audio, but also to disable HDMI_MODE_SELECT and video infoframe. Since
the DVI mode is mainly tied to audio functionality from end user POV,
add a new "force-dvi" audio mode:
xrandr --output HDMI1 --set audio force-dvi
Note that most users won't need to set this and happily rely on the EDID
based DVI auto detection.
Reported-by: Andrea Arcangeli <aarcange@redhat.com>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 53d227f282eb9fa4c7cdbfd691fa372b7ca8c4c3 |
|
25-Jan-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: fixup seqno allocation logic for lazy_request
Currently we reserve seqnos only when we emit the request to the ring
(by bumping dev_priv->next_seqno), but start using it much earlier for
ring->oustanding_lazy_request. When 2 threads compete for the gpu and
run on two different rings (e.g. ddx on blitter vs. compositor)
hilarity ensued, especially when we get constantly interrupted while
reserving buffers.
Breakage seems to have been introduced in
commit 6f392d548658a17600da7faaf8a5df25ee5f01f6
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Aug 7 11:01:22 2010 +0100
drm/i915: Use a common seqno for all rings.
This patch fixes up the seqno reservation logic by moving it into
i915_gem_next_request_seqno. The ring->add_request functions now
superflously still return the new seqno through a pointer, that will
be refactored in the next patch.
Note that with this change we now unconditionally allocate a seqno,
even when ->add_request might fail because the rings are full and the
gpu died. But this does not open up a new can of worms because we can
already leave behind an outstanding_request_seqno if e.g. the caller
gets interrupted with a signal while stalling for the gpu in the
eviciton paths. And with the bugfix we only ever have one seqno
allocated per ring (and only that ring), so there are no ordering
issues with multiple outstanding seqnos on the same ring.
v2: Keep i915_gem_get_seqno (but move it to i915_gem.c) to make it
clear that we only have one seqno counter for all rings. Suggested by
Chris Wilson.
v3: As suggested by Chris Wilson use i915_gem_next_request_seqno
instead of ring->oustanding_lazy_request to make the follow-up
refactoring more clearly correct. Also improve the commit message
with issues discussed on irc.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45181
Tested-by: Nicolas Kalkhof nkalkhof()at()web.de
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 67a3744f7515edda9888df5b226ec3b358908b42 |
|
09-Feb-2012 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: check gtfifodbg after possibly failed writes
If we don't have a sufficient number of free entries in the FIFO, we
proceed to do a write anyway. With this check we should have a clue if
that write actually failed or not.
After some discussion with Daniel Vetter regarding his original
complaint, we agreed upon this.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9edd576d89a5b6d3e136d7dcab654d887c0d25b7 |
|
10-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
Merge remote-tracking branch 'airlied/drm-fixes' into drm-intel-next-queued
Back-merge from drm-fixes into drm-intel-next to sort out two things:
- interlaced support: -fixes contains a bugfix to correctly clear
interlaced configuration bits in case the bios sets up an interlaced
mode and we want to set up the progressive mode (current kernels
don't support interlaced). The actual feature work to support
interlaced depends upon (and conflicts with) this bugfix.
- forcewake voodoo to workaround missed IRQ issues: -fixes only enabled
this for ivybridge, but some recent bug reports indicate that we
need this on Sandybridge, too. But in a slightly different flavour
and with other fixes and reworks on top. Additionally there are some
forcewake cleanup patches heading to -next that would conflict with
currrent -fixes.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
| e21af88d39796c907c38648c824be3d646ffbe35 |
|
09-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: enable ppgtt
We want to unconditionally enable ppgtt for two reasons:
- Windows uses this on snb and later.
- We need the basic hw support to work before we can think about real
per-process address spaces and other cool features we want.
But Chris Wilson was complaining all over irc and intel-gfx that this
will blow up if we don't have a module option to disable it. Hence add
one, to prevent this.
ppgtt support seems to slightly change the timings and make crashy
things slightly more or less crashy. Now in my testing and the testing
this got on troublesome snb machines, it seems to have improved things
only. But on ivb it makes quite a few crashes happen much more often,
see
https://bugs.freedesktop.org/show_bug.cgi?id=41353
Luckily Eugeni Dodonov seems to have a set of workarounds that fix
this issue.
v2: Don't try to enable ppgtt on pre-snb.
v3: Pimp commit message and make Chris Wilson less grumpy by adding a
module option.
v4: New try at making Chris Wilson happy.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7bddb01fb9697afd5d39bb69dd9f782a28063101 |
|
09-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: ppgtt binding/unbinding support
This adds support to bind/unbind objects and wires it up. Objects are
only put into the ppgtt when necessary, i.e. at execbuf time.
Objects are still unconditionally put into the global gtt.
v2: Kill the quick hack and explicitly pass cache_level to ppgtt_bind
like for the global gtt function. Noticed by Chris Wilson.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1d2a314c97ceaf383de8e23cdde46729927d433c |
|
09-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: initialization/teardown for the aliasing ppgtt
This just adds the setup and teardown code for the ppgtt PDE and the
last-level pagetables, which are fixed for the entire lifetime, at
least for the moment.
v2: Kill the stray debug printk noted by and improve the pte
definitions as suggested by Chris Wilson.
v3: Clean up the aperture stealing code as noted by Ben Widawsky.
v4: Paint the init code in a more pleasing colour as suggest by Chris
Wilson.
v5: Explain the magic numbers noticed by Ben Widawsky.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7e3b8737e719c4de7dd79b096b80ece444b2f0ba |
|
01-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: dump even more into the error_state
Chris Wilson and me have again stared at funny error states and it's
been pretty clear from the start that something was seriously amiss.
The seqnos last seen by the cpu were a few hundred behind those that
the gpu could have possibly emitted last before it died ...
Chris now tracked it down (hopefully, definit verdict's still out),
but in hindsight we'd have found the bug by simply dumping the cpu
side tracking of the ring head and tail registers.
Fix this and prevent an identical time-waster in the future.
Because the hangs always involved semaphores in one way or another,
we've tried to dump the mbox registers, but couldn't find any
inconsistencies. Still, dump them too.
Reviewed-and-wanted-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| f691e2f4cec334e906f971471b3bf1460c6256d4 |
|
02-Feb-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: swizzling support for snb/ivb
We have to do this manually. Somebody had a Great Idea.
I've measured speed-ups just a few percent above the noise level
(below 5% for the best case), but no slowdows. Chris Wilson measured
quite a bit more (10-20% above the usual snb variance) on a more
recent and better tuned version of sna, but also recorded a few
slow-downs on benchmarks know for uglier amounts of snb-induced
variance.
v2: Incorporate Ben Widawsky's preliminary review comments and
elaborate a bit about the performance impact in the changelog.
v3: Add a comment as to why we don't need to check the 3rd memory
channel.
v4: Fixup whitespace.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 33f3f518fbb65d86f163083b74823e8bbe561bfc |
|
14-Dec-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: add per-ring fault reg to error_state
This was pretty handy when figuring out what exactly went wrong with
ppgtt and it might also be useful when we stop filling the entire gart
with scratch page entries.
Also add the gen6+ DONE reg while at it.
v2: Chris Wilson suggested to allocate the error_state with kzalloc
for better paranoia. Also kill existing spurious clears of the
error_state while at it.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1690e1eb7a9021826853e181baa48dd77090da28 |
|
14-Dec-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Separate fence pin counting from normal bind pin counting
In order to correctly account for reserving space in the GTT and fences
for a batch buffer, we need to independently track whether the fence is
pinned due to a fenced GPU access in the batch or whether the buffer is
pinned in the aperture. Currently we count the fenced as pinned if the
buffer has already been seen in the execbuffer. This leads to a false
accounting of available fence registers, causing frequent mass evictions.
Worse, if coupled with the change to make i915_gem_object_get_fence()
report EDADLK upon fence starvation, the batchbuffer can fail with only
one fence required...
Fixes intel-gpu-tools/tests/gem_fenced_exec_thrash
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38735
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Paul Neumann <paul104x@yahoo.de>
[danvet: Resolve the functional conflict with Jesse Barnes sprite
patches, acked by Chris Wilson on irc.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| c1cd90ed7957d1dd8aa6138468d71003fbc095ce |
|
14-Dec-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: collect more per ring error state
Based on a patch by Ben Widawsky, but with different colors
for the bikeshed.
In contrast to Ben's patch this one doesn't add the fault regs.
Afaics they're for the optional page fault support which
- we're not enabling
- and which seems to be unsupported by the hw team. Recent bspec
lacks tons of information about this that the public docs released
half a year back still contain.
Also dump ring HEAD/TAIL registers - I've recently seen a few
error_state where just guessing these is not good enough.
v2: Also dump INSTPM for every ring.
v3: Fix a few really silly goof-ups spotted by Chris Wilson.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| d27b1e0ec2a0a04770b2ebf70a2e01281ef93562 |
|
14-Dec-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: refactor ring error state capture to use arrays
The code already got unwieldy and we want to dump more per-ring
registers.
Only functional change is that we now also capture the video
ring registers on ilk.
v2: fixup a refactor fumble spotted by Chris Wilson.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| b93f9cf14e714c20ce9a544ed1a6070ee7604588 |
|
26-Jan-2012 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: argument to control retiring behavior
Sometimes it may be the case when we idle the gpu or wait on something
we don't actually want to process the retiring list. This patch allows
callers to choose the behavior.
Reviewed-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9f1f46a45a681d357d1ceedecec3671a5ae957f4 |
|
14-Dec-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: protect force_wake_(get|put) with the gt_lock
The problem this patch solves is that the forcewake accounting
necessary for register reads is protected by dev->struct_mutex. But the
hangcheck and error_capture code need to access registers without
grabbing this mutex because we hold it while waiting for the gpu.
So a new lock is required. Because currently the error_state capture
is called from the error irq handler and the hangcheck code runs from
a timer, it needs to be an irqsafe spinlock (note that the registers
used by the irq handler (neglecting the error handling part) only uses
registers that don't need the forcewake dance).
We could tune this down to a normal spinlock when we rework the
error_state capture and hangcheck code to run from a workqueue. But
we don't have any read in a fastpath that needs forcewake, so I've
decided to not care much about overhead.
This prevents tests/gem_hangcheck_forcewake from i-g-t from killing my
snb on recent kernels - something must have slightly changed the
timings. On previous kernels it only trigger a WARN about the broken
locking.
v2: Drop the previous patch for the register writes.
v3: Improve the commit message per Chris Wilson's suggestions.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3d29b842e58fbca2c13a9f458fddbaa535c6e578 |
|
17-Jan-2012 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
drm/i915: add a LLC feature flag in device description
LLC is not SNB/IVB-specific, so we should check for it in a more generic
way.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| b2c606fe1defd1fb79612b48b528b2568c97def7 |
|
17-Jan-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: kill i915_mem.c
Some decent history digging indicates that this was to be used for the
GLX_MESA_allocate_memory extension but never actually implemented for
any released i915 userspace code.
So just rip it out.
v2: Fixup the Makefile.
Acked-by: Dave Airlie <airlied@gmail.com>
Cc: Keith Whitwell <keithw@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| b840d907fcf6d5d5ef91af4518b3dab3a5da0f75 |
|
13-Dec-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add SNB and IVB video sprite support v6
The video sprites support various video surface formats natively and can
handle scaling as well. So add support for them using the new DRM core
sprite support functions.
v2: use drm specific fourcc header and defines
v3: address Daniel's comments:
- don't take struct mutex around register access (only needed for
regs in the GT power well)
- don't hold struct mutex across vblank waits
- fix up update_plane API (pass obj instead of GTT offset)
- add interlaced defines for sprite regs
- drop unnecessary 'reg' variables
- comment double buffered reg flushing
Also fix w/h confusion when writing the scaling reg.
v4: more fixes, address more comments from Daniel, and include Hai's fix
- prevent divide by zero in scaling calculation (Hai Lan)
- update to Ville's new DRM_FORMAT_* types
- fix sprite watermark handling (calc based on CRTC size, separate
from normal display wm)
- remove private refcounts now that the fb cleanups handles things
v5: add linear surface support
v6: remove color key clearing & setting from update_plane
For this version, I tested DPMS since it came up in the last review;
DPMS off/on works ok when a video player is working under X, but for
power saving we'll probably want to do something smarter. I'll leave
that for a separate patch on top. Likewise with the refcounting/fb
layer handling, which are really separate cleanups.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| c7dffff7cc8de748edf0e9f6571cdabecb198705 |
|
09-Dec-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Clean up multi-threaded forcewake patch
We learned that the ECOBUS register was inside the GT power well, and
so *did* need force wake to be read, so it gets removed from the list
of 'doesn't need force wake' registers.
That means the code reading ECOBUS after forcing the mt_force_wake
function to be called needs to use I915_READ_NOTRACE; it doesn't need
to do more force wake fun as it's already done it manually.
This also adds a comment explaining why the MT forcewake testing code
only needs to call mt_forcewake_get/put and not disable RC6 manually
-- the ECOBUS read will return 0 if the device is in RC6 and isn't
using MT forcewake, causing the test to work correctly.
Signed-off-by: Keith Packard <keithp@keithp.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 097354eb14fa94d31a09c64d640643f58e4a5a9a |
|
27-Nov-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: check ACTHD of all rings
Otherwise hangcheck spuriously fires when running blitter/bsd-only
workloads.
Contrary to a similar patch by Ben Widawsky this does not check
INSTDONE of the other rings. Chris Wilson implied that in a failure to
detect a hang, most likely because INSTDONE was fluctuating. Thus only
check ACTHD, which as far as I know is rather reliable. Also, blitter
and bsd rings can't launch complex tasks from a single instruction
(like 3D_PRIM on the render with complex or even infinite shaders).
This fixes spurious gpu hang detection when running
tests/gem_hangcheck_forcewake on snb/ivb.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| f45b55575cedb7efa782e43f1ea74338456d0381 |
|
10-Dec-2011 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
drm/i915: enable semaphores on per-device defaults
This adds a default setting for semaphores parameter, and enables
semaphores by default on IVB.
For now, as semaphores interaction with VTd causes random issues on
SNB, we do not enable them by default. But they can still be enabled
via the semaphores=1 kernel parameter.
v2: enables semaphores on SNB when IO remapping is disabled, with base
on Keith Packard patch.
CC: Daniel Vetter <daniel.vetter@ffwll.ch>
CC: Ben Widawsky <ben@bwidawsk.net>
CC: Keith Packard <keithp@keithp.com>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42696
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40564
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38862
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| c0f372b3746d4ede07b2ace2beabd38d9c045b25 |
|
17-Nov-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: By default, enable RC6 on IVB and SNB when reasonable
RC6 should always work on IVB, and should work on SNB whenever IO
remapping is disabled. RC6 never works on Ironlake. Make the default
value for the parameter follow these guidelines. Setting the value
to either 0 or 1 will force the specified behavior.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38567
Cc: Ted Phelps <phelps@gnusto.com>
Cc: Peter <pab1612@gmail.com>
Cc: Lukas Hejtmanek <xhejtman@fi.muni.cz>
Cc: Andrew Lutomirski <luto@mit.edu>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4ed0b577457eb6aeb7cdc7e7316576e63d15abb2 |
|
10-Nov-2011 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
drm/i915: prevent division by zero when asking for chipset power
This prevents an in-kernel division by zero which happens when we are
asking for i915_chipset_val too quickly, or within a race condition
between the power monitoring thread and userspace accesses via debugfs.
The issue can be reproduced easily via the following command:
while ``; do cat /sys/kernel/debug/dri/0/i915_emon_status; done
This is particularly dangerous because it can be triggered by
a non-privileged user by just reading the debugfs entry.
This issue was also found independently by Konstantin Belousov
<kostikbel@gmail.com>, who proposed a similar patch.
Reported-by: Konstantin Belousov <kostikbel@gmail.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: <stable@vger.kernel.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8d715f0024f64ad1b1be85d8c081cf577944c847 |
|
19-Nov-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: add multi-threaded forcewake support
On IVB C0+ with newer BIOSes, the forcewake handshake has changed. There's
now a bitfield for different driver components to keep the GT powered
on. On Linux, we centralize forcewake handling in one place, so we
still just need a single bit, but we need to use the new registers if MT
forcewake is enabled.
This needs testing on affected machines. Please reply with your
tested-by if you had problems after a BIOS upgrade and this patch fixes
them.
v2: force MT mode. shift by 16
v3: set MT force wake bits then check ECOBUS
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42923
Tested-by: Manoj Iyer <manoj.iyer@canonical.com>
Tested-by: Robert Hooker <robert.hooker@canonical.com>
Tested-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4415e63b13c68c2f56d16d400a1ae345f68cf655 |
|
09-Nov-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Module parameters using '-1' as default must be signed type
Testing i915_panel_use_ssc for the default value was broken, so the
driver would never autodetect the correct value.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Michel Alexandre Salim <salimma@fedoraproject.org>
Tested-by: Michel Alexandre Salim <salimma@fedoraproject.org>
Cc: stable@kernel.org
/drivers/gpu/drm/i915/i915_drv.h
|
| 4b9de737fad5bd8993e6070530802de22f32744d |
|
09-Oct-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: add constants to size fence arrays and fields
In preparation of to support 32 fences on Ivybdrigde.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| f700088333c5c7e5a7f4ab71b642362290259e26 |
|
14-Oct-2011 |
Andi Kleen <ak@linux.intel.com> |
i915: Move i915_read/write out of line
With the tracing code in there they are far too big to inline.
.text savings compared to a non force inline kernel:
i915_restore_display 4393 12036 +7643
i915_save_display 4295 11459 +7164
i915_handle_error 2979 6666 +3687
i915_driver_irq_handler 2923 5086 +2163
i915_ringbuffer_info 458 1661 +1203
i915_save_vga - 1200 +1200
i915_driver_irq_uninstall 453 1624 +1171
i915_driver_irq_postinstall 913 2078 +1165
ironlake_enable_drps 719 1872 +1153
i915_restore_vga - 1142 +1142
intel_display_capture_error_state 784 2030 +1246
intel_init_emon 719 2016 +1297
and more ...
[AK: these are older numbers, with the new SNB forcewake checks
it will be even worse]
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 27f8227b1e2b326a9a0995dd9c1f14893c61ee01 |
|
02-Sep-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: support 3 pipes on IVB+
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI
interfaces, but only 2 pipe PLLs. So two of the pipes must use the same
pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode
and one other, etc.).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 46eb303682f72717d1a75cdd2309733bfed43396 |
|
16-Jun-2011 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Remove "i2c_speed" nonsense from child device table
I have no evidence for this byte being used this way, and lots of
counterexamples. Restore the struct to its empirical definition and
patch up gmbus setup to match.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9a1f57808afd65b1d066d5e1907526a1e45215df |
|
20-Oct-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'fix-pch-refclk' into foo
|
| 86a3073e480c522f12e5291a462f68f6ee30aee3 |
|
20-Oct-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'edp-training-fixes' into drm-intel-next
Conflicts:
drivers/gpu/drm/i915/intel_dp.c
Just whitespace change conflicts
|
| d15456de79eea2aa03cd277866db80556e984d49 |
|
19-Sep-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Move eDP panel fixed mode from dev_priv to intel_dp
This value doesn't come directly from the VBT, and so is rather
specific to the particular DP output.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| f01eca2e52169eaf3a485cbd9752435489fbfba9 |
|
29-Sep-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9fb526db979581841227e1ed4f75a5fbe853db4a |
|
27-Sep-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Initialize PCH refclks at modeset init time
The reference clock configuration must be done before any mode setting
can occur as all outputs must be disabled to change
anything. Initialize the clocks after turning everything off during
the initialization process.
Also, re-initialize the refclk at resume time.
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| abd06860185fc613776adae792772e076d77caf2 |
|
26-Sep-2011 |
Keith Packard <keithp@keithp.com> |
drv/i915: Pull display_clock_mode out of VBT table
This tells the driver whether a CK505 clock source is available on
pre-PCH hardware. If so, it should be used as the non-SSC source,
leaving the internal clock for use as the SSC source.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Chris Wison <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e0dac65ed45e72fe34cc7ccc76de0ba220bd38bb |
|
05-Sep-2011 |
Wu Fengguang <fengguang.wu@intel.com> |
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0206e353a0416ad63ce07f53c807c2c725633b87 |
|
16-Aug-2011 |
Akshay Joshi <me@akshayjoshi.com> |
Drivers: i915: Fix all space related issues.
Various issues involved with the space character were generating
warnings in the checkpatch.pl file. This patch removes most of those
warnings.
Signed-off-by: Akshay Joshi <me@akshayjoshi.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| aaa6fd2a004147bf32fce05720938236de3361d9 |
|
12-Aug-2011 |
Matthew Garrett <mjg@redhat.com> |
Not all systems expose a firmware or platform mechanism for changing the backlight intensity on i915, so add native driver support.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: David Airlie <airlied@linux.ie>
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Len Brown <lenb@kernel.org>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Sedat Dilek <sedat.dilek@googlemail.com>
Tested-by: Michel Alexandre Salim <salimma@fedoraproject.org>
Tested-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9b546e571b94cacccf1091cc9cc0bd8a6a207a66 |
|
30-Jul-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'drm-intel-fixes' into drm-intel-next
|
| cda2bb78c24de7674eafa3210314dc75bed344a6 |
|
26-Jul-2011 |
Adam Jackson <ajax@redhat.com> |
drm/i915/pch: Save/restore PCH_PORT_HOTPLUG across suspend
At least on a Lenovo X220 the HPD bits of this are enabled at boot but
cleared after resume, which means plug interrupts stop working.
This also happens to fix DP displays re-lighting on resume. I'm quite
certain that's an accident: the first DP link train inevitably fails on
that machine, and it's only serendipity that we're getting multiple plug
interrupts and the second train works. But I shall take my victories
where I get them.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Tested-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| df7976797fa9af161690dbf4dee81ed92cdc150f |
|
22-Jul-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'drm-intel-fixes' into drm-intel-next
|
| e28f87116503f796aba4fb27d81e2c3d81966174 |
|
18-Jul-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Fix unfenced alignment on pre-G33 hardware
Align unfenced buffers on older hardware to the power-of-two object
size. The docs suggest that it should be possible to align only to a
power-of-two tile height, but using the already computed fence size is
easier and always correct. We also have to make sure that we unbind
misaligned buffers upon tiling changes.
In order to prevent a repetition of this bug, we change the interface
to the alignment computation routines to force the caller to provide
the requested alignment and size of the GTT binding rather than assume
the current values on the object.
Reported-and-tested-by: Sitosfe Wheeler <sitsofe@yahoo.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36326
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 435793dfb8aec7b2e19f72d5bce8a22fd0b57839 |
|
12-Jul-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Add quirk to disable SSC on Lenovo U160 LVDS
We've tried several times to make this machine 'just work', but every
patch that does causes many other machines to fail. This adds a quirk
which special cases this hardware and forces ssc to be
disabled. There's no way to override this from the command line; that
would be a significantly more invasive change.
This patch fixes #36656 on fdo bugzilla:
https://bugs.freedesktop.org/show_bug.cgi?id=36656
Signed-off-by: Keith Packard <keithp@keithp.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=36656
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a35d9d3cf75604e9ef17faedd333bf2a66a513d8 |
|
13-Jul-2011 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: add module parameter compiler hints
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 95736720fc866eadb2ce1789631b907c0f38cb7c |
|
12-May-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Cache GT fifo count for SandyBridge
The read back of the available FIFO entries is vital for system
stability, but extremely costly. However, we only need a guide so as to
avoid eating into the reserved entries and since we are the only
consumer we can cache the read of the count from the last write.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 016b9b61ed692498a5d46dff974fe41b20e7e60b |
|
08-Jul-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Share the common work of disabling active FBC before updating
Upon review, all path share the same dependencies for updating the
registers and so we can benefit from sharing the code and checking
early.
This removes the unsightly intel_wait_for_vblank() from the lowlevel
functions and upon further analysis the only path that will require a
wait is if we are performing an instantaneous transition between two
valid FBC configurations. The page-flip path itself will have disabled
FBC registers and will have waited for at least one vblank before
finishing the flip and attempting to re-enable FBC. This wait can be
accomplished simply by delaying the enable until after we are sure that
a vblank will have passed, which we are already doing to make sure that
the display is settled before enabling FBC.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1630fe754c83b3e57efa51c85f1a21e612a63a0e |
|
08-Jul-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Perform intel_enable_fbc() from a delayed task
In order to accommodate the requirements of re-enabling FBC after
page-flipping, but to avoid doing so and incurring the cost of a wait
for vblank in the middle of a page-flip sequence, we defer the actual
enablement by 50ms. If any request to disable FBC arrive within that
interval, the enablement is cancelled and we are saved from blocking on
the wait.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 43a9539fa9e780f16c0d1e4bc91a2701f1ce178f |
|
08-Jul-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Only export the generic intel_disable_fbc() interface
As the enable/disable routines will be gain additional complexity in
future patches, it is necessary that all callers do not bypass the
generic interface by calling into the chipset routines directly. to do
this we make the chipset routines static, so there is no choice.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 17638cd68d5cbcd75dfad25966c0c56a5c2bac9f |
|
24-Jun-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split out plane update code
Updating the planes is device specific, so create a new display callback
and use it in pipe_set_base. (In fact we could go even further, valid
display plane bits have changed with each generation, as has tiled
buffer handling.)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| bee4d4acf563f91a7796cca53111d91be2532935 |
|
30-Jun-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'drm-intel-fixes' into drm-intel-next
|
| f71d4af4cd475aced6d9ec9730b03885ac80b833 |
|
28-Jun-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: move IRQ function table init to i915_irq.c
This lets us make the various IRQ functions static and helps avoid
problems like the one fixed in "drm/i915: Use chipset-specific irq
installers" where one of the exported functions was called rather than
the chipset specific version.
This also fixes a UMS-mode bug -- the correct irq functions for IRL
and later chips were only getting loaded in the KMS path.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| e489bda422b0a2c2cc33e598a4d400dfe654ad64 |
|
29-Jun-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'drm-intel-fixes' into drm-intel-next
|
| d70bed1947772f34d66ada3bd923bfc12ea2452b |
|
29-Jun-2011 |
Keith Packard <keithp@keithp.com> |
drm/i915: Hold struct_mutex during i915_save_state/i915_restore_state
Lots of register access in these functions, some of which requires the
struct mutex.
These functions now hold the struct mutex across the calls to
i915_save_display and i915_restore_display, and so the internal mutex
calls in those functions have been removed. To ensure that no-one else
was calling them (and hence violating the new required locking
invarient), those functions have been made static.
gen6_enable_rps locks the struct mutex, and so i915_restore_state
unlocks the mutex around calls to that function.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3e0dc6b01f5301d63046f6deddde2c7f5c57d67a |
|
29-Jun-2011 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: hangcheck disable parameter
Provide a parameter to disable hanghcheck. This is useful mostly for
developers trying to debug known problems, and probably should not be
touched by normal users.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8bc47de33569a111092a48465eb26cd855117e27 |
|
27-Jun-2011 |
Keith Packard <keithp@keithp.com> |
Merge branch 'drm-intel-fixes' into drm-intel-next
|
| 8c9f3aaf8e174ca914889ab7a916586f8fd1e641 |
|
16-Jun-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split page flip queueing into per-chipset functions
This makes things a little clearer and prevents us from running old code
on a new chipset that may not be supported.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewied-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2da3b9b940e2a18147422c54ed8b29d01e1ade88 |
|
14-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Combine pinning with setting to the display plane
We need to perform a few operations in order to move the object into the
display plane (where it can be accessed coherently by the display
engine) that are important for future safety to forbid whilst pinned. As a
result, we want to need to perform some of the operations before pinning,
but some are required once we have been bound into the GTT. So combine
the pinning performed by all the callers with set_to_display_plane(), so
this complication is contained within the single function.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| e4ffd173a1c2f96b43127c2537dd99d89e759bba |
|
04-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Add an interface to dynamically change the cache level
[anholt v2: Don't forget that when going from cached to uncached, we
haven't been tracking the write domain from the CPU perspective, since
we haven't needed it for GPU coherency.]
[ickle v3: We also need to make sure we relinquish any fences on older
chipsets and clear the GTT for sane domain tracking.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| a8198eea156df47e0e843ac5c7d4c8774e121c42 |
|
13-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Introduce i915_gem_object_finish_gpu()
... reincarnated from i915_gem_object_flush_gpu(). The semantic
difference is that after calling finish_gpu() the object no longer
resides in any GPU domain, and so will cause the GPU caches to be
invalidated if it is ever used again.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3f43c48d333777e815ae68d66396cb6dfbc2dd79 |
|
12-May-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Share the common force-audio property between connectors
Make the audio property creation routine common and share the single
property between the connectors.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4bce2da393dbbc6650a1d62683ef60e03594b4c7 |
|
12-May-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove unused enum "chip_family"
Superseded by the tracking the render generation in the chipset
capabiltiies struct.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| c1a9f047638b27e481d097910604316b8a0d132b |
|
06-May-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add fbc enable flag, but disable by default
FBC has too many corner cases that we don't currently deal with, so
disable it by default so we can enable more important features like RC6,
which conflicts in some configurations.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31742
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 645c62a5e95a5f9a8e0d0627446bbda4ee042024 |
|
11-May-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split PCH clock gating init
Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6067aaeadb5b3df26f27ac827256b1ef01e674f5 |
|
29-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| b1f14ad01ab09f5e22fb1240a6a158a23527ff14 |
|
06-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: interrupt & vblank support for Ivy Bridge
Add new interrupt handling functions for Ivy Bridge.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| eceae4817e01a16f1487d8b47ac2f56c68f3b330 |
|
06-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: Ivy Bridge has split display and pipe control
Ivy Bridge has a similar split display controller to Sandy Bridge, so
use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
use HAS_PIPE_CONTROL as well.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4b65177b27ede9dee3186bc3a58c737997ee4749 |
|
28-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add IS_IVYBRIDGE macro for checks
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 85436696fefd55afdf8f4ce26ac044be72f2d492 |
|
06-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
Note: IS_GEN* are for render related checks. Display and other checks
should use IS_MOBILE, IS_$CHIPSET or test for specific features.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| f796cf8f517f13826bb691432b03c7b5da13e530 |
|
07-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split enable/disable vblank code into chipset specific functions
This makes the Ironlake+ code trivial and generally simplifies things.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4697995b98417c6da9ab2708a36f5e2bc926c8ac |
|
07-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split irq handling into per-chipset functions
Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 674cf967614f31826f45d30c8f8f8e050cc3eef2 |
|
28-Apr-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: make FDI training a display function
Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4912d04193733a825216b926ffd290fada88ab07 |
|
25-Apr-2011 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: move gen6 rps handling to workqueue
The render P-state handling code requires reading from a GT register.
This means that FORCEWAKE must be written to, a resource which is shared
and should be protected by struct_mutex. Hence we can not manipulate
that register from within the interrupt handling and so must delegate
the task to a workqueue.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| fcca7926299944841569515da321bef9655b7703 |
|
25-Apr-2011 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: reference counted forcewake
Provide a reference count to track the forcewake state of the GPU and
give a safe mechanism for userspace to wake the GT. This also potentially
saves a UC read if the GT is known to be awake already.
The reference count is atomic, but the register access and hardware wake
sequence is protected by struct_mutex.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| b7287d8054d219b3009f7ca82edf24f89fd363e5 |
|
25-Apr-2011 |
Ben Widawsky <ben@bwidawsk.net> |
drm/i915: proper use of forcewake
Moved the macros around to properly do reads and writes for the given
GPU. This is to address special requirements for gen6 (SNB) reads and
writes.
Registers in the range 0-0x40000 on gen6 platforms require special
handling. Instead of relying on the callers to pick the registers
correctly, move the logic into the read and write functions.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2c7111dbaec72b01c804afb8ad77c6c7523986fd |
|
29-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Disable all outputs early, before KMS takeover
If the outputs are active and continuing to access the GATT when we
teardown the PTEs, then there is a potential for us to hang the GPU.
The hang tends to be a PGTBL_ER with either an invalid host access or
an invalid display plane fetch.
v2: Reorder IRQ initialisation to defer until after GEM is setup.
Reported-by: Pekka Enberg <penberg@kernel.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> (855GM)
Tested-by: Pekka Enberg <penberg@kernel.org>
# note that this doesn't fix the underlying problem of the
PGTBL_ER and pipe underruns being reported immediately upon
init on his 965GM MacBook
Reported-and-tested-by: Rick Bramley <richard.bramley@hp.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35635
Reported-and-tested-by: Zdenek Kabelac <zdenek.kabelac@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36048
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 93dfb40cd887c4f39e38f047c4d9ea0b7188a58a |
|
30-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Rename agp_type to cache_level
... to clarify just how we use it inside the driver and remove the
confusion of the poorly matching agp_type names. We still need to
translate through agp_type for interface into the fake AGP driver.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| f564048e201ead4d4d02138bc60ae28f83797ac4 |
|
30-Mar-2011 |
Eric Anholt <eric@anholt.net> |
drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines.
This path, which shouldn't be *that* complicated, is now so littered
with per-chipset tweaks that it's hard to trace the order of what
happens. HAS_PCH_SPLIT() is the most radical change across chipsets,
so it seems like a natural split to simplify the code.
This first commit just copies the existing code without changing
anything.
v2: updated to track removal of call to intel_enable_plane from i9xx_crtc_mode_set
Signed-off-by: Eric Anholt <eric@anholt.net>
Hella-acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 25985edcedea6396277003854657b5f3cb31a628 |
|
31-Mar-2011 |
Lucas De Marchi <lucas.demarchi@profusion.mobi> |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
/drivers/gpu/drm/i915/i915_drv.h
|
| 968b503e69a6b90aa4a3b9162960f605b6abd821 |
|
23-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Revert "drm/i915: Don't save/restore hardware status page address register"
This reverts commit a7a75c8f70d6f6a2f16c9f627f938bbee2d32718.
There are two different variations on how Intel hardware addresses the
"Hardware Status Page". One as a location in physical memory and the
other as an offset into the virtual memory of the GPU, used in more
recent chipsets. (The HWS itself is a cacheable region of memory which
the GPU can write to without requiring CPU synchronisation, used for
updating various details of hardware state, such as the position of
the GPU head in the ringbuffer, the last breadcrumb seqno, etc).
These two types of addresses were updated in different locations of code
- one inline with the ringbuffer initialisation, and the other during
device initialisation. (The HWS page is logically associated with
the rings, and there is one HWS page per ring.) During resume, only the
ringbuffers were being re-initialised along with the virtual HWS page,
leaving the older physical address HWS untouched. This then caused a
hang on the older gen3/4 (915GM, 945GM, 965GM) the first time we tried
to synchronise the GPU as the breadcrumbs were never being updated.
Reported-and-tested-by: Linus Torvalds <torvalds@linux-foundation.org>
Reported-by: Jan Niehusmann <jan@gondor.com>
Reported-by: Justin P. Mattock <justinmattock@gmail.com>
Reported-and-tested-by: Michael "brot" Groh <brot@minad.de>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 34db18abd376b2075c760c38f0b861aed379415d |
|
14-Mar-2011 |
Dave Airlie <airlied@redhat.com> |
Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-next
* 'intel/drm-intel-next' of ../drm-next: (755 commits)
drm/i915: Only wait on a pending flip if we intend to write to the buffer
drm/i915/dp: Sanity check eDP existence
drm/i915: Rebind the buffer if its alignment constraints changes with tiling
drm/i915: Disable GPU semaphores by default
drm/i915: Do not overflow the MMADDR write FIFO
Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing"
drm/i915: Don't save/restore hardware status page address register
drm/i915: don't store the reg value for HWS_PGA
drm/i915: fix memory corruption with GM965 and >4GB RAM
Linux 2.6.38-rc7
Revert "TPM: Long default timeout fix"
drm/i915: Re-enable GPU semaphores for SandyBridge mobile
drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"
Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU"
drm/i915: Allow relocation deltas outside of target bo
drm/i915: Silence an innocuous compiler warning for an unused variable
fs/block_dev.c: fix new kernel-doc warning
ACPI: Fix build for CONFIG_NET unset
mm: <asm-generic/pgtable.h> must include <linux/mm_types.h>
x86: Use u32 instead of long to set reset vector back to 0
...
Conflicts:
drivers/gpu/drm/i915/i915_gem.c
|
| 47ae63e0c2e5fdb582d471dc906eb29be94c732f |
|
07-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Merge branch 'drm-intel-fixes' into drm-intel-next
Apply the trivial conflicting regression fixes, but keep GPU semaphores
enabled.
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem_execbuffer.c
|
| 467cffba85791cdfce38c124d75bd578f4bb8625 |
|
07-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Rebind the buffer if its alignment constraints changes with tiling
Early gen3 and gen2 chipset do not have the relaxed per-surface tiling
constraints of the later chipsets, so we need to check that the GTT
alignment is correct for the new tiling. If it is not, we need to
rebind.
Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a1656b9090f7008d2941c314f5a64724bea2ae37 |
|
04-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Disable GPU semaphores by default
Andi Kleen narrowed his GPU hangs on his Sugar Bay (SNB desktop) rev 09
down to the use of GPU semaphores, and we already know that they appear
broken up to Huron River (mobile) rev 08. (I'm optimistic that disabling
GPU semaphores is simply hiding another bug by the latency and
side-effects of the additional device interaction it introduces...)
However, use of semaphores is a massive performance improvement... Only
as long as the system remains stable. Enable at your peril.
Reported-by: Andi Kleen <andi-fd@firstfloor.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33921
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 91355834646328e7edc6bd25176ae44bcd7386c7 |
|
04-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Do not overflow the MMADDR write FIFO
Whilst the GT is powered down (rc6), writes to MMADDR are placed in a
FIFO by the System Agent. This is a limited resource, only 64 entries, of
which 20 are reserved for Display and PCH writes, and so we must take
care not to queue up too many writes. To avoid this, there is counter
which we can poll to ensure there are sufficient free entries in the
fifo.
"Issuing a write to a full FIFO is not supported; at worst it could
result in corruption or a system hang."
Reported-and-Tested-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34056
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a7a75c8f70d6f6a2f16c9f627f938bbee2d32718 |
|
02-Mar-2011 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Don't save/restore hardware status page address register
It's cleaned before saving and re-initialized after restoring.
So don't need to save/restore it. And also new chip has new address
for hardware status page register, don't write to old address.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4cbf74ccf8362e99b2bdf1e66112a480c79ecacf |
|
25-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: don't store the reg value for HWS_PGA
It is trivially computable from the real physical address so no need to
store both.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 60c8bdf64a80ebb0132172ea97bd54d7c7d36611 |
|
05-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU"
Using PM latency request turns out to be very fragile and only works for
some systems, depending upon the ACPI implementation. However, I've
stumbled across a promising bit in INSTPM: "Interrupt-Based AGPBUSY#".
This reverts commit b0b544cd37c060e261afb2cf486296983fcb56da.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e953fd7bb32f55309a96abd5ceba9cf68d221434 |
|
21-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Add support for limited color range of broadcast outputs
In order to prevent "crushed blacks" on TVs, the range of the RGB output
may be limited to 16-235. This used to be available through Xorg under
the "Broadcast RGB" option, so reintroduce support for KMS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34543
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| ce453d81cb0397aa7d5148984f51907e14072d74 |
|
21-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use a device flag for non-interruptible phases
The code paths for modesetting are growing in complexity as we may need
to move the buffers around in order to fit the scanout in the aperture.
Therefore we face a choice as to whether to thread the interruptible status
through the entire pinning and unbinding code paths or to add a flag to
the device when we may not be interrupted by a signal. This does the
latter and so fixes a few instances of modesetting failures under stress.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| fca874092597ef946b8f07031d8c31c58b212144 |
|
17-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Add a module parameter to ignore lid status
Seems like we are forever to be cursed with buggy firmware, so allow the
user to explicitly set the panel connection status.
Of secondary utility for cases where I run laptops with the lid closed,
but still want to configure the LVDS.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| fc9a2228ac208dc2b6033cfc6c56b6f7655fbdfa |
|
17-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Revert "drm/i915: Disable SSC for outputs other than LVDS or DP"
This reverts commit 633f2ea26665d37bb3c8ae30799aa14988622653 and the
attempted fix dcbe6f2b3d136995915e2f9ecc7d4f3b28f47b6c.
There is a single clock source used for both SSC (some LVDS and DP) and
non-SSC (VGA, DVI) outputs. So we need to be careful to only enable SSC
as necessary. However, fiddling with DREFCLK was causing DP links to be
dropped and we do not have a fix ready, so revert.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9035a97a32836d0e456ddafaaf249a844e6e4b5e |
|
16-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Merge branch 'drm-intel-fixes' into drm-intel-next
Grab the latest stabilisation bits from -fixes and some suspend and
resume fixes from linus.
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c
|
| ac66808814036b4c33dd98091b2176ae6157f1a8 |
|
09-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Disable RC6 on Ironlake
The automatic powersaving feature is once again causing havoc, with 100%
reliable hangs on boot and resume on affected machines.
Reported-by: Francesco Allertsen <fallertsen@gmail.com>
Reported-by: Gui Rui <chaos.proton@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9db4a9c7b2a3bd5b4952846bc0c2f58daa80ddd7 |
|
07-Feb-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: cleanup per-pipe reg usage
We had some conversions over to the _PIPE macros, but didn't get
everything. So hide the per-pipe regs with an _ (still used in a few
places for legacy) and add a few _PIPE based macros, then make sure
everyone uses them.
[update: remove usage of non-existent no-op macro]
[update 2: keep modesetting suspend/resume code, update to new reg names]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: stylistic cleanups for checkpatch and taste]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| db53a302611c06bde01851f61fa0675a84ca018c |
|
03-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Refine tracepoints
A lot of minor tweaks to fix the tracepoints, improve the outputting for
ftrace, and to generally make the tracepoints useful again. It is a start
and enough to begin identifying performance issues and gaps in our
coverage.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| ff72145badb834e8051719ea66e024784d000cb4 |
|
06-Feb-2011 |
Dave Airlie <airlied@redhat.com> |
drm: dumb scanout create/mmap for intel/radeon (v3)
This is just an idea that might or might not be a good idea,
it basically adds two ioctls to create a dumb and map a dumb buffer
suitable for scanout. The handle can be passed to the KMS ioctls to create
a framebuffer.
It looks to me like it would be useful in the following cases:
a) in development drivers - we can always provide a shadowfb fallback.
b) libkms users - we can clean up libkms a lot and avoid linking
to libdrm_*.
c) plymouth via libkms is a lot easier.
Userspace bits would be just calls + mmaps. We could probably
mark these handles somehow as not being suitable for acceleartion
so as top stop people who are dumber than dumb.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5a1e5b6c460dccfd189c7e962281c8cce75da728 |
|
29-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Override SDVO panel type in VBT
Judging by comments in the BIOS, if the SDVO LVDS option h40 is enabled,
then we are supposed to query the real panel type via Int15. We don't do
this and so for the Sony Vaio VGC-JS210J which has otherwise default
values, we choose the wrong mode.
This patch adds a driver option, i915.vbt_sdvo_panel_type, which can be
used to override the value in the VBT.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33691
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e2f973d58e80ba00bcfaa171169c42c710e7e826 |
|
27-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record all error ringbuffers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 21dd373486956d7789ffd878347c36efad16923d |
|
26-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Defer reporting EIO until we try to use the GPU
Instead of reporting EIO upfront in the entrance of an ioctl that may or
may not attempt to use the GPU, defer the actual detection of an invalid
ioctl to when we issue a GPU instruction. This allows us to continue to
use bo in video memory (via pread/pwrite and mmap) after the GPU has hung.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5d6135012e9a7aa8a9128145ed9315eb916feea2 |
|
25-Jan-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: use VDD AUX override to make panel power sequencing look better
Rather than power cycling the panel when there are no bits to display,
use the VDD AUX bit to power the panel up just enough for DP AUX
transactions to work. This prevents a bit of unnecessary ugliness as
mode sets occur on the panel.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| d210246ab1106d77df91a4185b9d3b75a63be81f |
|
24-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Refactor self-refresh watermark calculations
Move the plane->mode config to the point of use rather than repeatedly
querying the same information.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| bdd92c9ad287e03a2ec52f5a89c470cd5caae1c2 |
|
23-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Merge branch 'drm-intel-fixes' into drm-intel-next
Merge important suspend and resume regression fixes and resolve the
small conflict.
Conflicts:
drivers/gpu/drm/i915/i915_dma.c
|
| bee4a186c16bed0d7e91425ca9356c2e8c015f8d |
|
21-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915,agp/intel: Do not clear stolen entries
We can only utilize the stolen portion of the GTT if we are in sole
charge of the hardware. This is only true if using GEM and KMS,
otherwise VESA continues to access stolen memory.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Reported-by: Frederic Weisbecker <fweisbec@gmail.com>
Tested-by: Jiri Olsa <jolsa@redhat.com>
Tested-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a37f2f87edc1b6e5932becf6e51535d36b690f2a |
|
23-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove unused code: i915_enable_interrupt()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 633f2ea26665d37bb3c8ae30799aa14988622653 |
|
19-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Disable SSC for outputs other than LVDS or DP
For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we
must clear any enabling bits left-over from earlier outputs. And also
seems to correct the LVDS panel on the Lenovo U160.
However, at one point, it did cause an "ERROR failed to disable
trancoder". So prolonged testing on top of Jesse's refactored and
error-checking CRTC logic is desired.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 311bd68e024f9006db66cbadc3bd9f62fd663f4b |
|
13-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Trivial sparse fixes
Move code around and invoke iomem annotation in a few more places in
order to silence sparse. Still a few more iomem annotations to go...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| b0b544cd37c060e261afb2cf486296983fcb56da |
|
09-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU
945 class hardware has an interesting quirk in which the vblank
interrupt is not raised if the CPU is in a low power state. (We also
suspect that the memory bus is clocked to the CPU/c-state and not the
GPU so there are secondary starvation issues.) In order to prevent the
most obvious issue of the low of the vblank interrupt (stuttering
compositing that only updates when the mouse is moving) is to install a
PM QoS request to prevent low c-states whilst the GPU is active.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 01fe9dbde19a1a27b8ee63e2d964562962e1eb78 |
|
16-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use ACPI OpRegion to determine lid status
Admittedly, trusting ACPI or the BIOS at all to be correct is littered
with numerous examples where it is wrong. Maybe, just maybe, we will
have better luck using the ACPI OpRegion lid status...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a76150302d6e7ebc43e1a1ddaee7fd51db8da3b3 |
|
12-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Add a module option to override the use of SSC
In order to workaround the issue with LVDS not working on the Lenovo
U160 apparently due to using the wrong SSC frequency, add an option to
disable SSC.
Suggested-by: Lukács, Árpád <lukacs.arpad@gmail.com>
Bugzillla: https://bugs.freedesktop.org/show_bug.cgi?id=32748
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
/drivers/gpu/drm/i915/i915_drv.h
|
| 6fe4f14044f181e146cdc15485428f95fa541ce8 |
|
10-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/execbuffer: Reorder binding of objects to favour restrictions
As the mappable portion of the aperture is always a small subset at the
start of the GTT, it is allocated preferentially by drm_mm. This is
useful in case we ever need to map an object later. However, if you have
a large object that can consume the entire mappable region of the
GTT this prevents the batchbuffer from fitting and so causing an error.
Instead allocate all those that require a mapping up front in order to
improve the likelihood of finding sufficient space to bind them.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a779e5abda0367aa9d53c0931d9687743afe503d |
|
09-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record AGP memory type upon error
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| bcfb2e285827bf0cfea8bbfad18a4fca57fbabae |
|
07-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record the error batchbuffer on each ring
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 882417851a0f2e09e110038a13e88e9b5a100800 |
|
07-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Propagate error from flushing the ring
... in order to avoid a BUG() and potential unbounded waits.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| d5bb081b027b520f9e59b4fb8faea83a136ec15e |
|
05-Jan-2011 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: cleanup rc6 code
Cleanup several aspects of the rc6 code:
- misnamed intel_disable_clock_gating function (was only about rc6)
- remove commented call to intel_disable_clock_gating
- rc6 enabling code belongs in its own function (allows us to move the
actual clock gating enable call back into restore_state)
- allocate power & render contexts up front, only free on unload
(avoids ugly lazy init at rc6 enable time)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: checkpatch cleanup]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0f46832fab779a9a3314ce5e833155fe4cf18f6c |
|
04-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Mask USER interrupts on gen6 (until required)
Otherwise we may consume 20% of the CPU just handling IRQs whilst
rendering. Ouch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 47356eb67285014527a5ab87543ba1fae3d1e10a |
|
11-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/panel: Only record the backlight level when it is enabled
By tracking the current status of the backlight we can prevent recording
the value of the current backlight when we have disabled it. And so
prevent restoring it to 'off' after an unbalanced sequence of
intel_lvds_disable/enable.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=22672
Tested-by: Alex Riesen <raa.lkml@gmail.com>
Tested-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
/drivers/gpu/drm/i915/i915_drv.h
|
| 72bfa19c8deb4d1db5ad068c34fd580cb295cbe8 |
|
19-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Allow the application to choose the constant addressing mode
The relative-to-general state default is useless as it means having to
rewrite the streaming kernels for each batch. Relative-to-surface is
more useful, as that stream usually needs to be rewritten for each
batch. And absolute addressing mode, vital if you start streaming
state, is also only available by adjusting the register...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3b8d8d91d51c7d15cda51052624169edf7b6dbc6 |
|
17-Dec-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: dynamic render p-state support for Sandy Bridge
Add an interrupt handler for switching graphics frequencies and handling
PM interrupts. This should allow for increased performance when busy
and lower power consumption when idle.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0af7e4dff50454905092d468e91c1ef92e10e6b4 |
|
08-Dec-2010 |
Mario Kleiner <mario.kleiner@tuebingen.mpg.de> |
drm/i915: Add support for precise vblank timestamping (v2)
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37
This patch adds new functions for use by the drm core:
.get_vblank_timestamp() provides a precise timestamp
for the end of the most recent (or current) vblank
interval of a given crtc, as needed for the DRI2
implementation of the OML_sync_control extension.
It is a thin wrapper around the drm function
drm_calc_vbltimestamp_from_scanoutpos() which does
almost all the work.
.get_scanout_position() provides the current horizontal
and vertical video scanout position and "in vblank"
status of a given crtc, as needed by the drm for use by
drm_calc_vbltimestamp_from_scanoutpos().
The patch modifies the pageflip completion routine
to use these precise vblank timestamps as the timestamps
for pageflip completion events.
This code has been only tested on a HP-Mini Netbook with
Atom processor and Intel 945GME gpu. The codepath for
(IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's
has not been tested so far due to lack of hardware.
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| eb43f4af7ecb7d51ba44f5e96bf74eedf1c27d62 |
|
08-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Terminate the FORCE WAKE after we have finished reading
Once we have read the value out of the GT power well, we need to remove
the FORCE WAKE bit to allow the system to auto-power down.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 67731b87e9572801c41f8fe779750babdd362416 |
|
08-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Eliminate drm_gem_object_lookup during relocation
As we provide a list of all objects that will be accessed from the
batchbuffer, we can build a lut of the handles associated with those
objects for this invocation and use that to avoid the overhead of
looking up those objects again for every relocation.
The cost of building and searching a small hash table is much less than
that of acquiring a spinlock, searching a radix tree and manipulating an
atomic refcnt per relocation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e3c4e5dd5ad1993a3687862c982272f8f00cae30 |
|
05-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: caps.has_rc6 is no longer used, remove it.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1ec14ad3132702694f2e1a90b30641cf111183b9 |
|
04-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNB
The bulk of the change is to convert the growing list of rings into an
array so that the relationship between the rings and the semaphore sync
registers can be easily computed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| d9e86c0ee60f323e890484628f351bf50fa9a15d |
|
10-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Pipelined fencing [infrastructure]
With this change, every batchbuffer can use all available fences (save
pinned and scanout, of course) without ever stalling the gpu!
In theory. Currently the actual pipelined update of the register is
disabled due to some stability issues. However, just the deferred update
is a significant win.
Based on a series of patches by Daniel Vetter.
The premise is that before every access to a buffer through the GTT we
have to declare whether we need a register or not. If the access is by
the GPU, a pipelined update to the register is made via the ringbuffer,
and we track the last seqno of the batches that access it. If by the
CPU we wait for the last GPU access and update the register (either
to clear or to set it for the current buffer).
One advantage of being able to pipeline changes is that we can defer the
actual updating of the fence register until we first need to access the
object through the GTT, i.e. we can eliminate the stall on set_tiling.
This is important as the userspace bo cache does not track the tiling
status of active buffers which generate frequent stalls on gen3 when
enabling tiling for an already bound buffer.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 87ca9c8a7ea9c8c7ce1561edaad1aa8570f1a01e |
|
02-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Prevent stalling for a GTT read back from a read-only GPU target
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c4e7a4146798ce22c229dd21ed31f59f07c4119e |
|
30-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/ringbuffer: Handle cliprects in the caller
This makes the various rings more consistent by removing the anomalous
handing of the rendering ring execbuffer dispatch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 432e58edc9de1d9c3d6a7b444b3c455b8f209a7d |
|
25-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Avoid allocation for execbuffer object list
Besides the minimal improvement in reducing the execbuffer overhead, the
real benefit is clarifying a few routines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 54cf91dc4e51fd5070a9a2346377493cc38a1ca9 |
|
25-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Split i915_gem_execbuffer into its own file.
A number of dragons have been seen lurking within the execbuffer code.
The first step is then to isolate them from the rest and begin to
scrutinise them in depth. Suggested by Daniel Vetter.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6299f992c0491232f008028a1f40bc9d86c4c76c |
|
24-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Defer accounting until read from debugfs
Simply remove our accounting of objects inside the aperture, keeping
only track of what is in the aperture and its current usage. This
removes the over-complication of BUGs that were attempting to keep the
accounting correct and also removes the overhead of the accounting on
the hot-paths.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2021746e1d5ad1e3b51e24480c566acbb833c7c1 |
|
23-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Mark a few functions as __must_check
... to benefit from the compiler checking that we remember to handle
and propagate errors.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| caea7476d48e5f401f2d18b1738827748fb56c12 |
|
12-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: More accurately track last fence usage by the GPU
Based on a patch by Daniel Vetter.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 919926aeb3e89825093c743dd54f04e42e7d9150 |
|
12-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Thread the pipelining ring through the callers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 576ae4b8e46b4cb9d5390f4348c265329793d9bf |
|
12-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Extend hangcheck timeout
... reduce the frequency of checking to further reduce the wakeups and
CPU overhead.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| b6913e4bdb09134dbdccd613e880d413b5911591 |
|
12-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Move the implementation details of PIPE_CONTROL to the ringbuffer
The pipe control object is allocated by the device for the sole use of the
render ringbuffer. Move this detail from the general code to the render
ring buffer initialisation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 748ebc6017a943ec065e653e975a5e8dace77ac6 |
|
24-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record fence registers on error.
Having seen the effects of erroneous fencing on the batchbuffer, a
useful sanity check is to record the fence registers at the time of an
error.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 05394f3975dceb107a5e1393e2244946e5b43660 |
|
08-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use drm_i915_gem_object as the preferred type
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and
many characters!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 185cbcb304ba4dee55e39593fd86dcd7813f62ec |
|
06-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: no more agp for gem
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7c2e6fdf452cddeff6a8ee5156edba39e53246fc |
|
06-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: move gtt handling to i915_gem_gtt.c
No more drm_*_agp in i915_gem.c!
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 76aaf22016caa7764f40e792aaca7b4918312b22 |
|
05-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: restore gtt on resume in the drm instead of in intel-gtt.ko
This still uses the agp functions to actually reinstate the mappings
(with a gross hack to make agp cooperate), but it wires everything
up correctly for the switchover.
The call to agp_rebind_memory can be dropped because all non-kms drivers
do all their rebinding on EnterVT.
v2: Be more paranoid and flush the chipset cache after restoring gtt
mappings.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 93a37f20eabeea4039130527b07453038c07f471 |
|
05-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: track objects in the gtt
This is required to restore gtt mappings on resume when agp is gone.
The right way to do this would be to make sturct drm_mm_node embeddable
and use the allocation list maintained by the drm memory manager. But
that's a bigger project. Getting rid of the per bo agp_mem will save
more memory than this wastes, anyway.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c64f7ba5f1006d8c20eacafecf98d4d00a6902a0 |
|
23-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
agp/intel: Remove confusion of stolen entries not stolen memory
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| fe669bf88e9108b96a847385df08c9b1e98c1420 |
|
23-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Compute physical addresses from base of stolen memory
The GATT is a write-only set of registers, reading from them in the
manner of i915_gtt_to_phys() is supposed to be undefined. However a
simple solution exists as we allocate linear memory from the stolen
area, we can simply add the block offset to the base register. As a
side-effect we recover all the unused stolen GTT entries and so enlarge
our aperture.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5f75377db4d8d81ca4465b54d3c339c70c6a0fa2 |
|
22-Nov-2010 |
Keith Packard <keithp@keithp.com> |
drm/i915: Fix restore of 965 fence regs since the register tracing change.
We were reading our 64-bit value in I915_READ64 and returning 32 bits
of it. The restoration of fence regs at resume then had a zero end
value, and the fence had no effect.
Version 2: Split register access functions into per-size versions
Sharing code between different sizes seemed reasonable when we only
needed a single copy, but as 64-bit access requires its own version,
it makes sense to just split them out for each size.
Reported-by: Peter Clifton <pcjc2@cam.ac.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
[ickle: use a macro to create the various read/write routines]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c4a1d9e4dc5d5313cfec2cc0c9d630efe8a6f287 |
|
21-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Capture interesting display registers on error
When trying to diagnose mysterious errors on resume, capture the
display register contents as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c724e8a9407683a8a2ee8eb00b972badf237bbe1 |
|
22-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Capture pinned buffers on error
The pinned buffers are useful for diagnosing errors in setting up state
for the chipset, which may not necessarily be 'active' at the time of
the error, e.g. the cursor buffer object.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c94f28c383f58c9de74678e0f1624db9c5f8a8cb |
|
15-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
Merge branch 'drm-intel-fixes' into drm-intel-next
Conflicts:
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/intel_ringbuffer.c
|
| 85345517fe6d4de27b0d6ca19fef9d28ac947c4a |
|
13-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Retire any pending operations on the old scanout when switching
An old and oft reported bug, is that of the GPU hanging on a
MI_WAIT_FOR_EVENT following a mode switch. The cause is that the GPU is
waiting on a scanline counter on an inactive pipe, and so waits for a
very long time until eventually the user reboots his machine.
We can prevent this either by moving the WAIT into the kernel and
thereby incurring considerable cost on every swapbuffers, or by waiting
for the GPU to retire the last batch that accesses the framebuffer
before installing a new one. As mode switches are much rarer than swap
buffers, this looks like an easy choice.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28964
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29252
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
/drivers/gpu/drm/i915/i915_drv.h
|
| cae5852dcaa1139b198e13ebd3aeb7f3c065f875 |
|
09-Nov-2010 |
Zou Nan hai <nanhai.zou@intel.com> |
drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring register
Before reading ring register, set FORCE_WAKE bit to prevent GT core
power down to low power state, otherwise we may read stale values.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[ickle: added a udelay which seemed to do the trick on my SNB]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 527f9e907c39f7e88abb57eaa8bccb43c8706a3d |
|
11-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove the global irq wait queue
... as it has been replaced by per-ring waiters.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 374c479bef7ecd2b41d6dd6e24aa21d73b3afae5 |
|
08-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: POSTING_READs are simply flushes and so irrelevant to tracing
As we use POSTING_READ to flush the write to the register before
proceeding, we do not care what the return value is and similar we do
not care for the read to be recorded whilst tracing register
read/writes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 65e5ecb066fe54c13c8445d6acfdcdf149ad5df9 |
|
08-Nov-2010 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
drm/i915: Add untraced register read/write interface
This will be used later to hide the frequently written registers
from debug traces in order to increase the signal-to-noise.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| ba4f01a30480cdcd516b782f77a6e0951b83df1c |
|
08-Nov-2010 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
drm/i915: trace down all the register write and read
Add two tracepoints at I915_WRITE/READ for tracing down all the
register write and read.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 75e9e9158f38e5cb21eff23b30bafa6f32e0a606 |
|
04-Nov-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: kill mappable/fenceable disdinction
a00b10c360b35d6431a "Only enforce fence limits inside the GTT" also
added a fenceable/mappable disdinction when binding/pinning buffers.
This only complicates the code with no pratical gain:
- In execbuffer this matters on for g33/pineview, as this is the only
chip that needs fences and has an unmappable gtt area. But fences
are only possible in the mappable part of the gtt, so need_fence
implies need_mappable. And need_mappable is only set independantly
with relocations which implies (for sane userspace) that the buffer
is untiled.
- The overlay code is only really used on i8xx, which doesn't have
unmappable gtt. And it doesn't support tiled buffers, currently.
- For all other buffers it's a bug to pass in a tiled bo.
In short, this disdinction doesn't have any practical gain.
I've also reverted mapping the overlay and context pages as possibly
unmappable. It's not worth being overtly clever here, all the big
gains from unmappable are for execbuf bos.
Also add a comment for a clever optimization that confused me
while reading the original patch by Chris Wilson.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 46168f39360f419e59952d58cd08a862886ec8cd |
|
04-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
Merge branch 'drm-intel-fixes' into drm-intel-next
|
| e07ac3a0b17ed9dec26b742ea41514063ef12386 |
|
04-Nov-2010 |
Zhenyu Wang <zhenyu.z.wang@intel.com> |
drm/i915; Don't apply Ironlake FDI clock workaround to Sandybridge
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 328fc1325f144027f4a8269b11e9f8dcf1edcb97 |
|
02-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
Revert "drm/i915: add MMIO debug output"
We can use mmiotrace instead of our own debug printks.
This reverts commit be282fd48e7492812402a22d73a348c44bf95b63.
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
/drivers/gpu/drm/i915/i915_drv.h
|
| 0f8c6d7ca9257d6a01671ab69b897860d3ae9bc0 |
|
01-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Move the invalidate|flush information out of the device struct
... and into a local structure scoped for the single function in which
it is used.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e5c652603680404683fd1f262b511340545179a2 |
|
01-Nov-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/debugfs: Report ring in error state
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5eac3ab45955b32f3a9d89e633918c4d6f133dfa |
|
31-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Evict just the purgeable GTT entries on the first pass
Take two passes to evict everything whilst searching for sufficient free
space to bind the batchbuffer. After searching for sufficient free space
using LRU eviction, evict everything that is purgeable and try again.
Only then if there is insufficient free space (or the GTT is too badly
fragmented) evict everything from the aperture and try one last time.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| add354ddf62beac55ca3ba64835dd703a0649867 |
|
29-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record BSD engine error state
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1d8f38f4e7146d22f7fbc94eef0508bd75463f54 |
|
29-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record BLT engine error state
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a00b10c360b35d6431a94cbf130a4e162870d661 |
|
24-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Only enforce fence limits inside the GTT.
So long as we adhere to the fence registers rules for alignment and no
overlaps (including with unfenced accesses to linear memory) and account
for the tiled access in our size allocation, we do not have to allocate
the full fenced region for the object. This allows us to fight the bloat
tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside
the GTT we still suffer the additional alignment constraints, so it doesn't
magic allow us to render larger scenes without stalls -- we need the
expanded GTT and fence pipelining to overcome those...]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e5281ccd2e0049e2b9e8ce82449630d25082372d |
|
28-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Eliminate nested get/put pages
By using read_cache_page() for individual pages during pwrite/pread we
can eliminate an unnecessary large allocation (and immediate free) of
obj->pages. Also this eliminates any potential nesting of get/put pages,
simplifying the code and preparing the path for greater things.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 39a01d1fb63cf8ebc1a8cf436f5c0ba9657b55c6 |
|
28-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove mmap_offset
Since we rarely use the mmap_offset and it is easily computable from the
obj->map_list.hash, remove it.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 17250b71553680bc6e927497aa619ab06ab1015b |
|
28-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Make the inactive object shrinker per-device
Eliminate the racy device unload by embedding a shrinker into each
device. Smaller, simpler code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| f406839f094ef24bb201c9574fdb9ce8e799a975 |
|
27-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Capture ERROR register on Sandybridge hangs
This holds error state from the main graphics arbiter mainly involving
the DMA engine and address translation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| fb7d516af11837126eb1e4a44ab0653bf9b57702 |
|
01-Oct-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: add accounting for mappable objects in gtt v2
More precisely: For those that _need_ to be mappable. Also add two
BUG_ONs in fault and pin to check the consistency of the mappable
flag.
Changes in v2:
- Add tracking of gtt mappable space (to notice mappable/unmappable
balancing issues).
- Improve the mappable working set tracking by tracking fault and pin
separately.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 53984635a659e360f206a81ada4ae813152d72f1 |
|
22-Sep-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: use the complete gtt
At least the part that's currently enabled by the BIOS.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 920afa77ced7124c8bb7d0c4839885618a3b4a54 |
|
16-Sep-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: range-restricted bind_to_gtt
Like before add a parameter mappable (also to gem_object_pin) and
set it depending upon the context. Only bos that are brought into
the gtt due to an execbuffer call can be put into the unmappable
part of the gtt, everything else (especially pinned objects) need
to be put into the mappable part of the gtt.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a6e0aa421406dc4cfd736c6d07d26ed39ab4f7bc |
|
16-Sep-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: range-restricted eviction support
Add a mappable parameter to i915_gem_evict_something to distinguish
the two cases (non-restricted vs. mappable gtt allocations). No
functional changes because the mappable limit is set to the end of
the gtt currently.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3cce469cab880ef8990d2d16d745bf85443fc998 |
|
27-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Propagate error from failing to queue a request
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| b2223497b44a4701d1be873d1e9453d7f720043b |
|
27-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove the confusing global waiting/irq seqno
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e1f99ce6cac3b6a95551642be5ddb5d9c46bea76 |
|
27-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Propagate errors from writing to ringbuffer
Preparing the ringbuffer for adding new commands can fail (a timeout
whilst waiting for the GPU to catch up and free some space). So check
for any potential error before overwriting HEAD with new commands, and
propagate that error back to the user where possible.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 78501eac34f372bfbeb4e1d9de688c13efa916f6 |
|
27-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/ringbuffer: Drop the redundant dev from the vfunc interface
The ringbuffer keeps a pointer to the parent device, so we can use that
instead of passing around the pointer on the stack.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 641934069d29211baf82afb93622a426172b67b6 |
|
24-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Move gpu_write_list to per-ring
... to prevent flush processing of an idle (or even absent) ring.
This fixes a regression during suspend from 87acb0a5.
Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net>
Tested-by: Peter Clifton <pcjc2@cam.ac.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| f00a3ddf91d596bece5fa31e8ce2e8a3b4c0623b |
|
21-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: IS_IRONLAKE is synonymous with gen == 5
So remove the redundant bit in the capabilities block and
s/IS_IRONLAKE/IS_GEN5/.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 549f7365820a212a1cfd0871d377b1ad0d1e5723 |
|
19-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Enable SandyBridge blitter ring
Based on an original patch by Zhenyu Wang, this initializes the BLT ring for
SandyBridge and enables support for user execbuffers.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 69dc4987cbe5fe70ae1c2a08906d431d53cdd242 |
|
19-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Track objects in global active list (as well as per-ring)
To handle retirements, we need per-ring tracking of active objects.
To handle evictions, we need global tracking of active objects.
As we enable more rings, rebuilding the global list from the individual
per-ring lists quickly grows tiresome and overly complicated. Tracking the
active objects in two lists is the lesser of two evils.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 896673836b8c55b75e7d7d2741aaaadff0c6a038 |
|
08-Oct-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915/dp: cache eDP DPCD data
Cache the first 4 bytes of DPCD data in the eDP case. It's unlikely to
change and can save us some trouble at link training time.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9f0e7ff4b366d27570cbe0ffa137ed1018009114 |
|
08-Oct-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: fetch eDP configuration data from the VBT
We need to use some of these values in eDP configurations, so be sure to
fetch them and store them in the i915 private structure.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 723bfd707a97fee06eb3ba4d3e8b4714c29a1064 |
|
08-Oct-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add _DSM support
The _DSM method on the integrated graphics device can tell us which
connectors are muxable, so add support for making the call and parsing
out the connector info.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: fix compiler warnings for using uninitialized 'result' and
downgrade error message for non-switchable devices]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| ae681d969ac0946e09636f2bef7a126d73e1ad6b |
|
01-Oct-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: If the GPU hangs twice within 5 seconds, declare it wedged.
The issue is that we may become stuck executing a long running shader
and continually attempt to reset the GPU. (Or maybe we tickle some bug
and need to break the vicious cycle.) So if we are detect a second hang
within 5 seconds, give up trying to programme the GPU and report it
wedged.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 069efc1dac477a4a51e42c0fe50bdcf85ada626a |
|
30-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Clear fence registers on GPU reset
When the GPU is reset, the fence registers are invalidated, so release
the objects and clear them out.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 73aa808f10effc280e6eb70267314542a7c29426 |
|
30-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm: Move the GTT accounting to i915
Only drm/i915 does the bookkeeping that makes the information useful,
and the information maintained is driver specific, so move it out of the
core and into its single user.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5cdf58817433345157644140f2f509f00c06d479 |
|
27-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Make get/put pages static
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 23bc598253fa8e9ede6ad29304ea4ed177e9fc23 |
|
29-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/debug: Convert i915_verify_active() to scan all lists
... and check more regularly.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3d2a812ae4676b74f2033cf09c855074d06f3872 |
|
29-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/debug: Remove default WATCH_BUF
Replaced by tracepoints.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 97d1ebaf81491afd8b45186056eda7ebf5da7875 |
|
29-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/debug: Remove defunct WATCH_LRU
This has bitrotted through inuse and superseded by tracing and debugfs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| b8232e906381dcba2bb26f0d849d4c25cc9b1368 |
|
28-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Disable LVDS i2c probing when using GPIO bit banging
This check only appears to succeed when using GMBUS, so we need to skip
it if we have fallen back to using GPIO bit banging.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e957d7720a2797b31231616014b68f4f6203145e |
|
24-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/sdvo: Fix GMBUSification
Besides a couple of bugs when writing more than a single byte along the
GMBUS, SDVO was completely failing whilst trying to use GMBUS, so use
bit banging instead.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1c25595f8d31392b8c36b54c624d01591dbfb87b |
|
26-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Convert the file mutex into a spinlock
Daniel Vetter pointed out that in this case is would be clearer and
cleaner to use a spinlock instead of a mutex to protect the per-file
request list manipulation. Make it so.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 30dbf0c07ff4e3e21b827e2a9d6ff7eb34458819 |
|
25-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Adjust hangcheck EIO semantics
Owain Ainsworth reported an issue between the interaction of the
hangcheck and userspace immediately (and permanently) falling back to
s/w rasterisation. In order to break the mutex and begin resetting the
GPU, we must abort the current operation (usually within the wait) and
climb sufficiently far back up the call chain to drop the mutex. In his
implementation, Owain has a loop within the ioctl handler to detect the
hang and then sleep until the error handler has run. I've chosen to
return to userspace and report an EAGAIN which should trigger the
userspace ioctl handler to repeat the call (simply because it felt less
invasive...). Before hitting a wedged GPU, we then wait upon completion
of the error handler.
Reported-by: Owain G. Ainsworth <zerooa@googlemail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| f787a5f59e1b0e320a6b0a37e9a2e306551d1e40 |
|
24-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Only hold a process-local lock whilst throttling.
Avoid cause latencies in other clients by not taking the global struct
mutex and moving the per-client request manipulation a local per-client
mutex. For example, this allows a compositor to schedule a page-flip
(through X) whilst an OpenGL application is monopolising the GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5ceb0f9bb7bde101d8b07cb803002591dcb8c804 |
|
24-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Parse the eDP link configuration from the vBIOS
First step, lets have a look at the values for troublesome panels and
see if they may be used to improve our link training.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| e6c3a2a6d358a726c2c52cb0132c9ad8f6f37486 |
|
24-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use an uninterruptible wait for page-flips during modeset
We need to drain the pending flips prior to disabling the pipe during
modeset, and these need to be done in an uninterruptible fashion.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| d3849eded23e6c78b19acc1a3a7811a01d2f541d |
|
23-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove unused dev_priv->panel_wants_dither
This is now private to the DVO connector, remove it from the main device
private.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 20f0cd55f68e0678909214c60b3595a22124bdb0 |
|
23-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove the broken flush_ring from page-flip
This is already performed with the pipelined flush, so by the time we
schedule the flush in the page-flip, the ring is NULL and we OOPs
instead.
Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| dfaae392f4461785eb1c92aeaf2a1040b184edba |
|
22-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Clear the gpu_write_list on resetting write_domain upon hang
Otherwise we will hit a list handling assertion when moving the object
to the inactive list.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| f13d3f7311add99d1f874a6b67d56426afa35664 |
|
20-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Track pinned objects
Keep a list of pinned objects and display it via debugfs. Now all
objects that exist in the GTT are always tracked on one of the
active, flushing, inactive or pinned lists.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 265db9585e570814d2f7aca109c5563bcde9c948 |
|
20-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Drain any pending flips on the fb prior to unpinning
If we have queued a page flip on the current fb and then request a mode
change, wait until the page flip completes before performing the new
request.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c78ec30bba52754b9f21a899eac2e2f5a7486116 |
|
20-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Merge ring flushing and lazy requests
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 53640e1d07fb7dd5d14300dd94f4718eca33348e |
|
20-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Track gpu fence usage
Track if the gpu requires the fence for the execution of a batch buffer
and so only wait upon the retirement of the object's last rendering
seqno if the fence is in use by the GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c7f9f9a8b89bb4d53edc030f5b61ae11d6859721 |
|
19-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use ring->flush() instead of MI_FLUSH
Use the ring abstraction to hide the details of having choose the
appropriate flushing method.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 92f49d9cec0052e09d938ac913d8e9ab432a0584 |
|
16-Sep-2010 |
Xiang, Haihao <haihao.xiang@intel.com> |
drm/i915: fix HAS_BSD with a device info flag
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| f803aa5532d14efc463abbeae10faa115c457a07 |
|
19-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Clean up bo lists on all hung gpus
Previously we only tidied up the active bo lists for chipsets were we
would attempt to reset the GPU. However, this action is necessary for
the system to continue and reclaim the dead bo for all chipsets.
Pointed out, in passing, by Owain Ainsworth.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 77f01230223a08792f5320ebba27af9cbb81b0cf |
|
19-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Clear GPU read domains on reset
Clear the GPU read domain for the inactive objects on a reset so that
they are correctly invalidated on reuse.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9375e446e7f43be9a7c21e246cee35ea912532ec |
|
19-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Clear flushing lists on GPU reset
Owain Ainsworth noticed that the reset code failed to clear the flushing
list leaving the driver in an inconsistent state following a hung GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9220434a8768902cd9cf248709972678b74aa8c1 |
|
18-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Only emit a flush request on the active ring.
When flushing the GPU domains,we emit a flush on *both* rings, even
though they share a unified cache. Only emit the flush on the currently
active ring.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a6c45cf013a57e32ddae43dd4ac911eb4a3919fd |
|
17-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g
Avoid confusion between i965g meaning broadwater and the gen4+ chipset
families.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| f899fc64cda8569d0529452aafc0da31c042df2e |
|
21-Jul-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: use GMBUS to manage i2c links
Use the GMBUS interface rather than direct bit banging to grab the EDID
over DDC (and for other forms of auxiliary communication with external
display controllers). The hope is that this method will be much faster
and more reliable than bit banging for fetching EDIDs from buggy monitors
or through switches, though we still preserve the bit banging as a
fallback in case GMBUS fails.
Based on an original patch by Jesse Barnes.
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2cf34d7b7ee99c27c1a6bdd2f91344cbfa5fef5c |
|
14-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Allow get_fence_reg() to be uninterruptible
As we currently may need to acquire a fence register during a modeset,
we need to be able to do so in an uninterruptible manner. So expose that
parameter to the callers of the fence management code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 48b956c5a89c7b100ef3b818b6ccf759ab695383 |
|
14-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Push pipelining of display plane flushes to the caller
This ensures that we do wait upon the flushes to complete if necessary
and avoid the visual tears, whilst enabling pipelined page-flips.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7213342db58adb7b8e399a00fc423951d7f75369 |
|
14-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Consolidate flushing the display plane
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| b3b079dbef06c7f775178d561a4c8e47b7447139 |
|
14-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Reduce hangcheck frequency
By reducing the hangcheck frequency we check less often, conserving
resources, and still detect a lock up quickly. On a fast machine with a
slow GPU (like a Core2 paired with a 945G) it is easy for the hangcheck to
misfire as we check too fast.
Also once hung and if we fail to completely reset the chip, we have a
nasty habit of proclaming a hang many times a second and generating a
strobe-like display.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 788319d48dc2b61db732b19bb9598c062c75ec37 |
|
12-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/lvds: Move private data to the connector from the device.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| bed4a6734b5f56ffd240fdda755b6eb589d32482 |
|
11-Sep-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Fix updating FBC
We need to track different state on each generation in order to detect
when we need to refresh the FBC registers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 19966754328d99ee003ddfc7a8c31ceb115483ac |
|
06-Sep-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: die, i915_probe_agp, die
Use the detection from intel-gtt.ko instead. Hooray!
Also move the stolen mem allocator to the other gtt stuff in dev_prv->mem.
v2: Chris Wilson noted that my error handling was crap. Fix it. He also
said that this fixes a problem on his i845. Indeed, i915_probe_agp
misses a special case for i830/i845 stolen mem detection.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25476
Cc: stable@kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0ade638655f0ef4d807295c14a4c97544bd6b9ca |
|
24-Aug-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
intel-gtt: introduce drm/intel-gtt.h
Add a few definitions to it that are already shared and that will
be shared in the future (like the number of stolen entries).
No functional changes in here.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a95735569312f2ab0c80425e2cd1e5cb0b4e1870 |
|
22-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Refactor panel backlight controls
There were two instances of code to control the panel backlight and
neither handled the complete set of device variations.
Fixes:
Bug 29716 - [GM965] Regression: Backlight resets to minimum when changing resolution
https://bugs.freedesktop.org/show_bug.cgi?id=29716
And a bug on one of my PineView boxes which overflowed the backlight
value.
Incorporates part of a similar patch by Matthew Garrett that exposes a
native Intel backlight controller.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| de227ef0907258359d53e3e1530c1f3678eb2bb9 |
|
03-Jul-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Kill the active list spinlock
This spinlock only served debugging purposes in a time when we could not
be sure of the mutex ever being released upon a GPU hang. As we now
should be able rely on hangcheck to do the job for us (and that error
reporting should not itself require the struct mutex) we can kill the
incomplete attempt at protection.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3bd3c9329973a93fa3ef5e9840f2fd6fa2889e3f |
|
19-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Compile out error state without DEBUG_FS
Alexander reported that the compilation of intel_overlay.c was failing
due to an inclusion that was only valid with CONFIG_DEBUG_FS. As the
whole error reporting is only useful with debugfs enabled, remove all
the redundant error state collection code when compiling without
CONFIG_DEBUG_FS.
Reported-by: Alexander Lam <lambchop468@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8dc5d14741dc1ee0074a14b360993a10c2c02d24 |
|
12-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Preallocate requests
By allocating the request prior to writing to the ringbuffer, we can
abort the operation without leaving the GPU in an inconsistent state.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 31578148b2c62612f9516fdcf5ebb64ab32ed12d |
|
12-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915/overlay: Move capabilities bits to common info block.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8a1a49f954734040dbc7b87e3b1221a050045e43 |
|
11-Feb-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: move flushing list processing to i915_retire_commands
... instead of threading flush_domains through the execbuf code to
i915_add_request.
With this change 2 small cleanups are possible (likewise the majority
of the patch):
- The flush_domains parameter of i915_add_request is always 0. Drop it
and the corresponding logic.
- Ditto for the seqno param of i915_gem_process_flushing_list.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| a6910434e1b5f2a9fe7cab39b01bae9a7a7bbe70 |
|
02-Feb-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: only one interrupt per batchbuffer is not enough!
Previously I thought that one interrupt per batchbuffer should be
enough. Now tedious benchmarking showed this to be wrong.
Therefore track whether any commands have been isssued with a future
seqno (like pipelined fencing changes or flushes). If this is the case
emit a request before issueing the batchbuffer.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| be282fd48e7492812402a22d73a348c44bf95b63 |
|
14-Aug-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add MMIO debug output
Useful for capturing register read/write traces to send to the hw guys.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 44834a67c0082e2cf74b16be91e49108b1432d65 |
|
19-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use the VBT from OpRegion when available (v3)
It is recommended that we use the Video BIOS tables that were copied
into the OpRegion during POST when initialising the driver. This saves
us from having to furtle around inside the ROM ourselves and possibly
allows the vBIOS to adjust the tables prior to initialisation.
On some systems, such as the Samsung N210, there is no accessible VBIOS
and the only means of finding the VBT is through the OpRegion.
v2: Rearrange the code so that ASLE is enabled along with ACPI
v3: Enable OpRegion parsing even without ACPI
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Garrett <mjg@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3b61796785e7b0ca8846b7a709216dceb6e2f68d |
|
24-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Rename i915_opregion.c to intel_opregion.c
It's part of the generic Intel driver infrastructure so rename it in
prepreparation for using it for VBT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 75ef9da2cdb64e7926404dd2b755bbbfe98eaeaf |
|
21-Aug-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: unload: fix retire_work races
ums-gem code correctly cancels the retire work (at lastclose time),
kms does not do so. Fix this by canceling the work right after ideling
the gpu.
While staring at the code I noticed that the work function is not
static. Fix this, too.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946 |
|
11-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Include a generation number in the device info
To simplify the IS_GEN[234] macros and to enable switching.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| aa40d6bbb9cf88f3fb296a57e046a52e9a68ab72 |
|
25-Jun-2010 |
Zou Nan hai <nanhai.zou@intel.com> |
drm/i915: Set up a render context on Ironlake
RC6 power state requires a logical render context in place for saving
render context.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6eeefaf3c86b8937db8ad930c48bfb592fc5e32e |
|
07-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Apply i830 errata for cursor alignment
i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose
the alignment parameter to i915_gem_attach_phys_object().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1d8e1c75ffa84400758aef9cc59298920b8801f9 |
|
07-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Enable aspect/centering panel fitting for Ironlake.
v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| cd377ea93f34cbd6ec49c868b66a5a7ab184775c |
|
07-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Implement fair lru eviction across both rings. (v2)
Based in a large part upon Daniel Vetter's implementation and adapted
for handling multiple rings in a single pass.
This should lead to better gtt usage and fixes the page-fault-of-doom
triggered. The fairness is provided by scanning through the GTT space
amalgamating space in rendering order. As soon as we have a contiguous
space in the GTT large enough for the new object (and its alignment),
evict any object which lies within that space. This should keep more
objects resident in the GTT.
Doing throughput testing on a PineView machine with cairo-perf-trace
indicates that there is very little difference with the new LRU scan,
perhaps a small improvement... Except oddly for the poppler trace.
Reference:
Bug 15911 - Intermittent X crash (freeze)
https://bugzilla.kernel.org/show_bug.cgi?id=15911
Bug 20152 - cannot view JPG in firefox when running UXA
https://bugs.freedesktop.org/show_bug.cgi?id=20152
Bug 24369 - Hang when scrolling firefox page with window in front
https://bugs.freedesktop.org/show_bug.cgi?id=24369
Bug 28478 - Intermittent graphics lockups due to overflow/loop
https://bugs.freedesktop.org/show_bug.cgi?id=28478
v2: Attempt to clarify the logic and order of eviction through the use
of comments and macros.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b47eb4a2b302f33adaed2a27d2b3bfc74fe35ac5 |
|
07-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Move the eviction logic to its own file.
The eviction code is the gnarly underbelly of memory management, and is
clearer if kept separated from the normal domain management in GEM.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6f392d548658a17600da7faaf8a5df25ee5f01f6 |
|
07-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use a common seqno for all rings.
This will be used by the eviction logic to maintain fairness between the
rings.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6ef3d4278034982c13df87c4a51e0445f762d316 |
|
04-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Capture the overlay status upon a GPU hang.
v2: Add the interrupt status and address.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| dbd7ac9661ba321fe9c1f1b7cb5f4471a6e59570 |
|
04-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use an uncommon name for the local dev_priv in macros
Using dev_priv__ avoids sparse complaining about shadowed variables in
the *LP_RING() macros.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 88f356b725c8a18c4da3ee0b6dcbc647418268f2 |
|
04-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Only emit flushes on active rings.
This avoids the excess flush and requests on idle rings (and spamming
the debug log ;-)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| be72615bcf4d5b7b314d836c5e1b4baa4b65dad1 |
|
24-Jul-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Repeat unbinding during free if interrupted (v6)
If during the freeing of an object the unbind is interrupted by a system
call, which is quite possible if we have outstanding GPU writes that
must be flushed, the unbind is silently aborted. This still leaves the
AGP region and backing pages allocated, and perhaps more importantly,
the object remains upon the various lists exposing us to memory
corruption.
I think this is the cause behind the use-after-free, such as
Bug 15664 - Graphics hang and kernel backtrace when starting Azureus
with Compiz enabled
https://bugzilla.kernel.org/show_bug.cgi?id=15664
v2: Daniel Vetter reminded me that kernel space programming is never easy.
We cannot simply spin to clear the pending signal and so must deferred
the freeing of the object until later.
v3: Run from the top level retire requests.
v4: Tested with P(return -ERESTARTSYS)=.5 from i915_gem_do_wait_request()
v5: Rebase against Eric's for-linus tree.
v6: Refactor, split and add a comment about avoiding unbounded recursion.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b09a1feca65764311f8a3e14befb52b98d705f0a |
|
24-Jul-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Refactor i915_gem_retire_requests()
Combine the iteration over active render rings into a common function.
This is in preparation for reusing the idle function to also retire
deferred free requests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2bd34f6ca86b5a5f9b749624f73310820e7a93fd |
|
02-Aug-2010 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/master' into drm-intel-next
This resolves the conflict in the EDP code, which has been rather
popular to hack on recently.
Conflicts:
drivers/gpu/drm/i915/intel_dp.c
|
| 534843dabf79da40561148764916e1b2e6bbcebe |
|
05-Jul-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Use 128k alignment for untiled display surface on i965 (v2)
The original i965, including the revised G35 and Q35, requires an
alignment of 128K for the display surface with linear memory, so
increase the requirement from 64k for these chipsets. For the later
chipsets in the i965 family, only a 4k alignment is required. (So
long as we do not start performing asynchronous flips.)
Note the impact of this should be slight as on i965 we should be using a
tiled frontbuffer for anything up to a 4096x4096 display.
v2: compilation fixes and note that the docs do not exclude the G35 from
the extra alignment.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| cbb465e72ae2cf37d252284c28a0d89ddfaaa240 |
|
06-Jun-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Include instdone[1] in hangcheck
References:
Bug 26691 - Spurious hangcheck whilst executing a long shader over a
large vertex buffer
https://bugs.freedesktop.org/show_bug.cgi?id=26691
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| d312ec251769dc2ad6c9bd9856a756c6097ab63c |
|
06-Jun-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Sparse warns about the incorrect sign for storing bit17
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 11824e8c4e8a1279ee209173da777b2295b72e82 |
|
06-Jun-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Silence sparse complaints over insufficient bitfield int types.
drivers/gpu/drm/i915/i915_drv.h|676 col 19| warning: dubious bitfield without explicit `signed' or `unsigned'
drivers/gpu/drm/i915/i915_drv.h|712 col 19| warning: dubious bitfield without explicit `signed' or `unsigned'
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2dafb1e082c541d4bc0f275a6ffa9c39da690f01 |
|
07-Jun-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Propagate error from i915_gem_object_flush_gpu_write_domain()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b52eb4dcab23fe0c52a437276258e0afcf913ef5 |
|
12-Jun-2010 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Add frame buffer compression support on Ironlake mobile
About 0.2W power can be saved on one HP laptop.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| fa143215b11056b878875f87edac78a1cfb9d1c0 |
|
12-Jun-2010 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Fix watermark calculation in self-refresh mode
For self-refresh mode WM calculation's "line time" should use
mode's htotal instead of hdisplay. "surface width" is the hdisplay
for display plane and 64 for cursor plane.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b690e96cf9e6a6cde6f0393de47bdd6317ddb5de |
|
19-Jul-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add pipe A force quirks to i915 driver
Ported over from the old UMS list. Unfortunately they're still
necessary especially on older laptop platforms.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=22126.
Tested-by: Xavier <shiningxc@gmail.com>
Tested-by: Diego Escalante Urrelo <diegoe@gnome.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9c928d168d4030a230a7a5ee1764721d173f1153 |
|
24-Jul-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: disable FBC when more than one pipe is active
We're really supposed to do this to avoid trouble with underflows when
multiple planes are active.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=26987.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: fangxun <xunx.fang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 97e0214044d9f279a3d6286c9f859696ef0b7ebe |
|
02-Jul-2010 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: fix page flip finish vs. prepare on plane B
drm/i915: change default panel fitting mode to preserve aspect ratio
drm/i915: fix uninitialized variable warning in i915_setup_compression()
drm/i915: take struct_mutex in i915_dma_cleanup()
drm/i915: Fix CRT hotplug regression in 2.6.35-rc1
i915: fix ironlake edp panel setup (v4)
drm/i915: don't access FW_BLC_SELF on 965G
drm/i915: Account for space on the ring buffer consumed whilst wrapping.
drm/i915: gen3 page flipping fixes
drm/i915: don't queue flips during a flip pending event
drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
drm/i915: Turn on 945 self-refresh only if single CRTC is active
drm/i915/gen4: Fix interrupt setup ordering
drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection.
drm/i915: Move non-phys cursors into the GTT
Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)."
(Included the "fix page flip finish vs. prepare on plane B" patch from
Jesse on top of the pull request from Eric. -- Linus)
|
| 1afe3e9d4335bf3bc5615e37243dc8fef65dac8f |
|
26-Mar-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: gen3 page flipping fixes
Gen3 chips have slightly different flip commands, and also contain a bit
that indicates whether a "flip pending" interrupt means the flip has
been queued or has been completed.
So implement support for the gen3 flip command, and make sure we use the
flip pending interrupt correctly depending on the value of ECOSKPD bit
0.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| be26a10bd10271b4a810ece2e540c0cdd77881bc |
|
12-Jun-2010 |
Zou Nan hai <nanhai.zou@intel.com> |
drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
The ring_begin API was taking a number of bytes, while all of our
other begin/end macros take number of dwords. Change the API over to
dwords to prevent future bugs.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| a3524f1b27671eda909cde37da9caff41133b272 |
|
06-Jun-2010 |
Dave Airlie <airlied@redhat.com> |
drm/i915: fix oops on single crtc devices.
(regression fix since fbdev/kms rework).
My fb rework didn't remember about the 84/65s.
Reported-by: Ondrej Zary <linux@rainbow-software.org>
Tested-by: Ondrej Zary <linux@rainbow-software.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| e20f9c64c79e2282f9eb531509181965ec8f0a92 |
|
26-May-2010 |
Eric Anholt <eric@anholt.net> |
drm/i915: Clean up leftover bits from hws move to ring structure.
Fixes /debug/dri/0/i915_gem_interrupt output for status page.
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9553426372eef71c849499fb1d232f4b0577c0f9 |
|
18-May-2010 |
Li Peng <peng.li@linux.intel.com> |
drm/i915: Add CxSR support on Pineview DDR3
Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.
Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 778c35444f7bbb8f1816d40ada650e19c5da9c02 |
|
13-May-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: combine all small integers into one single bitfield
This saves a whooping 7 dwords. Zero functional changes. Because
some of the refcounts are rather tightly calculated, I've put
BUG_ONs in the code to check for overflows.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7648fa99eb77a2e1a90b7beaa420e07d819b9c11 |
|
20-May-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add power monitoring support
Add power monitoring support to the i915 driver for use by the IPS
driver. Export the available power info to the IPS driver through a few
new inter-driver hooks. When used together, the IPS driver and this
patch can significantly increase graphics performance on Ironlake class
chips.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Fixed 32-bit compile. stupid obfuscating div_u64()]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| d1b851fc0d105caa6b6e3e7c92d2987dfb52cbe0 |
|
21-May-2010 |
Zou Nan hai <nanhai.zou@intel.com> |
drm/i915: implement BSD ring buffer V2
The BSD (bit stream decoder) ring is used for accessing the BSD engine
which decodes video bitstream for H.264 and VC1 on G45+. It is
asynchronous with the render ring and has access to separate parts of
the GPU from it, though the render cache is coherent between the two.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 852835f343146a82a528c3b712b373661d4fa17a |
|
21-May-2010 |
Zou Nan hai <nanhai.zou@intel.com> |
drm/i915: convert some gem structures to per-ring V2
The active list and request list move into the ringbuffer structure,
so each can track its active objects in the order they are in that
ring. The flushing list does not, as it doesn't matter which ring
caused data to end up in the render cache. Objects gain a pointer to
the ring they are active on (if any).
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8187a2b70e34c727a06617441f74f202b6fefaf9 |
|
21-May-2010 |
Zou Nan hai <nanhai.zou@intel.com> |
drm/i915: introduce intel_ring_buffer structure (V2)
Introduces a more complete intel_ring_buffer structure with callbacks
for setup and management of a particular ringbuffer, and converts the
render ring buffer consumers to use it.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
[anholt: Fixed up whitespace fail and rebased against prep patches]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| d3301d86b4bf2bcf649982ae464211d8bcf9575a |
|
21-May-2010 |
Eric Anholt <eric@anholt.net> |
drm/i915: Rename dev_priv->ring to dev_priv->render_ring.
With the advent of the BSD ring, be clear about which ring this is.
The docs are pretty consistent with calling this the Render engine at
this point.
/drivers/gpu/drm/i915/i915_drv.h
|
| 62fdfeaf8b1f487060b6e160e7b5cd90287607c9 |
|
21-May-2010 |
Eric Anholt <eric@anholt.net> |
drm/i915: Move ringbuffer-related code to intel_ringbuffer.c.
This is preparation for supporting multiple ringbuffers on Ironlake.
The non-copy-and-paste changes are:
- de-staticing functions
- I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files.
- i915_gem_add_request had only half its implementation
copy-and-pasted out of the middle of it.
/drivers/gpu/drm/i915/i915_drv.h
|
| 007cc8ac4e0787fc7ad2e4585614800671d48d4e |
|
28-Apr-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: move fence lru to struct drm_i915_fence_reg
This lru tracks fences, not objects, so move it to where it belongs.
As a side effect, this nicely shrinks drm_i915_gem_object by two
pointers.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b1083333de5357577c5ec55df6c7efa17bee41c7 |
|
23-Apr-2010 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Fix DDC bus selection for multifunction SDVO
Multifunction SDVO cards stopped working after 14571b4, and would report
something that looked remarkably like an ADD2 SPD ROM instead of EDID.
This appears to be because DDC bus selection was utterly horked by that
commit; controlled_output was no longer always a single bit, so
intel_sdvo_select_ddc_bus would pick bus 0, which is (unsurprisingly)
the SPD ROM bus, not a DDC bus.
So, instead of that, let's just use the DDC bus the child device table
tells us to use. I'm guessing at the bitmask and shifting from VBIOS
dumps, but it can't possibly be worse.
cf. https://bugzilla.redhat.com/584229
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 34dc4d4423dc342848d72be764832cbc0852854a |
|
07-May-2010 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/master' into drm-intel-next
Conflicts:
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/radeon/r300.c
The BSD ringbuffer support that is landing in this branch
significantly conflicts with the Ironlake PIPE_CONTROL fix on master,
and requires it to be tested successfully anyway.
|
| ee5382aedf669127bf672a3fc5313247fc288e26 |
|
23-Apr-2010 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Make fbc control wrapper functions
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| e552eb7038a36d9b18860f525aa02875e313fe16 |
|
21-Apr-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control. On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.
So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.
https://bugs.freedesktop.org/show_bug.cgi?id=27108
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 20bf377e679208ba9ae0edcb8c70a8f6d33d17f9 |
|
21-Apr-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: cleanup FBC buffers at unload time
This keeps the memory manager from complaining when we take it down.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| a8089e849a32c5b6bfd6c88dbd09c0ea4a779b71 |
|
09-Apr-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: drop pointer to drm_gem_object
Luckily the change is quite a little bit less invasive than I've
feared.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 62b8b21515065235bd363ad07094d301532e14ce |
|
09-Apr-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: don't use ->driver_private anymore
Thanks to the to_intel_bo helper, this change is rather trivial.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| c397b9084cabdcaae26266bd0bd32ba62e757046 |
|
09-Apr-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: embed the gem object into drm_i915_gem_object
Just embed it and adjust the pointers, No other changes (that's
for later patches).
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| ac52bc56de25535a907ef07f8755f1387b89b0f5 |
|
09-Apr-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: introduce i915_gem_alloc_object
Just preparation, no functional change.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7fff400be6fbf64f10abca9939718aaf1d61c255 |
|
20-Apr-2010 |
Dave Airlie <airlied@redhat.com> |
Merge branch 'drm-fbdev-cleanup' into drm-core-next
* drm-fbdev-cleanup:
drm/fb: remove drm_fb_helper_setcolreg
drm/kms/fb: use slow work mechanism for normal hotplug also.
drm/kms/fb: add polling support for when nothing is connected.
drm/kms/fb: provide a 1024x768 fbcon if no outputs found.
drm/kms/fb: separate fbdev connector list from core drm connectors
drm/kms/fb: move to using fb helper crtc grouping instead of core crtc list
drm/fb: fix fbdev object model + cleanup properly.
Conflicts:
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/nouveau/nouveau_drv.h
|
| 5ce8ba7c9279a63f99e1f131602580472b8af968 |
|
15-Apr-2010 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Fix 82854 PCI ID, and treat it like other 85X
pci.ids and the datasheet both say it's 358e, not 35e8.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| e3421a189447c0b8cd0aff5c299f53b5ab7c38f6 |
|
08-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: enable DP/eDP for Sandybridge/Cougarpoint
DP on Cougarpoint has new training pattern definitions, and
new transcoder DP control register is used to determine the mapping
for transcoder and DP digital output. And eDP for Sandybridge has
new voltage and pre-emphasis level definitions.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3bad0781832e4e8c9a532f1169bfcd7257bcfd9e |
|
07-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Probe for PCH chipset type
PCH is the new name for south bridge from Ironlake/Sandybridge,
which contains most of the display outputs except eDP. This one
adds a probe function to detect current PCH type, and method to
detect Cougarpoint PCH.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7da9f6cbf70656ed1c913a674b82b68e076c99f7 |
|
07-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Sandybridge has no integrated TV
Integrated TV is deprecated in new chips from Ironlake.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| bfac4d6725baacbfc085c38e231b8582a1b8f62b |
|
07-Apr-2010 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Ignore LVDS EDID when it is unavailabe or invalid
This trys to shut up complains about invalid LVDS EDID during
mode probe, but uses fixed panel mode directly for panels with
broken EDID.
https://bugs.freedesktop.org/show_bug.cgi?id=23099
https://bugs.freedesktop.org/show_bug.cgi?id=26395
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Tested-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8be48d924c307e72e3797ab5bde81b07a1ccc52d |
|
30-Mar-2010 |
Dave Airlie <airlied@redhat.com> |
drm/kms/fb: move to using fb helper crtc grouping instead of core crtc list
This move to using the list of crtcs in the fb helper and cleans up the
whole picking code, now we store the crtc/connectors we want directly
into the modeset and we use the modeset directly to set the mode.
Fixes from James Simmons and Ben Skeggs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 386516744ba45d50f42c6999151cc210cb4f96e4 |
|
30-Mar-2010 |
Dave Airlie <airlied@redhat.com> |
drm/fb: fix fbdev object model + cleanup properly.
The fbdev layer in the kms code should act like a consumer of the kms services and avoid having relying on information being store in the kms core structures in order for it to work.
This patch
a) removes the info pointer/psuedo palette from the core drm_framebuffer structure and moves it to the fbdev helper layer, it also removes the core drm keeping a list of kernel kms fbdevs.
b) migrated all the fb helper functions out of the crtc helper file into the fb helper file.
c) pushed the fb probing/hotplug control into the driver
d) makes the surface sizes into a structure for ease of passing
This changes the intel/radeon/nouveau drivers to use the new helper.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 23010e43b353c2cdc9725cbedc7e364708039bf7 |
|
08-Mar-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: introduce to_intel_bo helper
This is a purely cosmetic change to make changes in this area easier.
And hey, it's not only clearer and typechecked, but actually shorter,
too!
[anholt: To clarify, this is a change to let us later make
drm_i915_gem_object subclass drm_gem_object, instead of having
drm_gem_object have a pointer to i915's private data]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 59f2d0fc4bdfbbfabfa3715ba17d0609e5964c7e |
|
09-Mar-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Fix check with IS_GEN6
IS_GEN6 missed to include SandyBridge mobile chip, which failed in
i915_probe_agp() for memory config detection. Fix it with a device
info flag.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1c62233508ef7104f8a78e571fdf5c72d0dc0200 |
|
01-Mar-2010 |
Dave Airlie <airlied@redhat.com> |
Merge branch 'gpu-switcher' of /ssd/git//linux-2.6 into drm-next-stage
* 'gpu-switcher' of /ssd/git//linux-2.6:
vga_switcheroo: initial implementation (v15)
fb: for framebuffer handover don't exit the loop early.
Conflicts:
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/radeon/Makefile
drivers/gpu/drm/radeon/radeon.h
|
| 6a9ee8af344e3bd7dbd61e67037096cdf7f83289 |
|
01-Feb-2010 |
Dave Airlie <airlied@linux.ie> |
vga_switcheroo: initial implementation (v15)
Many new laptops now come with 2 gpus, one to be used for low power
modes and one for gaming/on-ac applications. These GPUs are typically
wired to the laptop panel and VGA ports via a multiplexer unit which
is controlled via ACPI methods.
4 combinations of systems typically exist - with 2 ACPI methods.
Intel/ATI - Lenovo W500/T500 - use ATPX ACPI method
ATI/ATI - some ASUS - use ATPX ACPI Method
Intel/Nvidia - - use _DSM ACPI method
Nvidia/Nvidia - - use _DSM ACPI method.
TODO:
This patch adds support for the ATPX method and initial bits
for the _DSM methods that need to written by someone with
access to the hardware.
Add a proper non-debugfs interface - need to get some proper
testing first.
v2: add power up/down support for both devices
on W500 puts i915/radeon into D3 and cuts power to radeon.
v3: redo probing methods, no DMI list, drm devices call to
register with switcheroo, it tries to find an ATPX method on
any device and once there is two devices + ATPX it inits the
switcher.
v4: ATPX msg handling using buffers - should work on more machines
v5: rearchitect after more mjg59 discussion - move ATPX handling to
radeon driver.
v6: add file headers + initial nouveau bits (to be filled out).
v7: merge delayed switcher code.
v8: avoid suspend/resume of gpu that is off
v9: rearchitect - mjg59 is always right. - move all ATPX code to
radeon, should allow simpler DSM also proper ATRM handling
v10: add ATRM support for radeon BIOS, add mutex to lock vgasr_priv
v11: fix bug in resuming Intel for 2nd time.
v12: start fixing up nvidia code blindly.
v13: blindly guess at finishing nvidia code
v14: remove radeon audio hacks - fix up intel resume more like upstream
v15: clean up printks + remove unnecessary igd/dis pointers
mount debugfs
/sys/kernel/debug/vgaswitcheroo/switch - should exist if ATPX detected
+ 2 cards.
DIS - immediate change to discrete
IGD - immediate change to IGD
DDIS - delayed change to discrete
DIGD - delayed change to IGD
ON - turn on not in use
OFF - turn off not in use
Tested on W500 (Intel/ATI) and T500 (Intel/ATI)
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| bad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 |
|
23-Oct-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9df30794f609d9412f14cfd0eb7b45dd64d0b14e |
|
18-Feb-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Record batch buffer following GPU error
In order to improve our diagnostic capabilities following a GPU hang
and subsequent reset, we need to record the batch buffer that triggered
the error. We assume that the current batch buffer, plus a few details
about what else is on the active list, will be sufficient -- at the very
least an improvement over nothing.
The extra information is stored in /debug/dri/.../i915_error_state
following an error, and may be decoded using
intel_gpu_tools/tools/intel_error_decode.
v2: Avoid excessive work under spinlocks.
v3: Include ringbuffer for later analysis.
v4: Use kunmap correctly and record more buffer state.
v5: Search ringbuffer for current batch buffer
v6: Use a work fn for the impossible IRQ error case.
v7: Avoid non-atomic paths whilst in IRQ context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| f590d279eb4978352af163a88b001f156c7147d2 |
|
18-Feb-2010 |
Owain Ainsworth <zerooa@googlemail.com> |
drm/i915: reduce some of the duplication of tiling checking
i915_gem_object_fenceable was mostly just a repeat of the
i915_gem_object_fence_offset_ok, but also checking the size (which was
checkecd when we allowed that BO to be tiled in the first place). So
instead, export the latter function and use it in place.
Signed-Off-By: Owain G. Ainsworth <oga@openbsd.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b5e50c3f56ee4aa0d0168eab5ece413ac5df76aa |
|
05-Feb-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: provide FBC status in debugfs
Tools like powertop want to check the current FBC status and report it
to the user. So add a debugfs file indicating whether FBC is enabled,
and if not, why.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b5b72e891a5a6056c849ef8eaf259f126090f88b |
|
02-Feb-2010 |
Matthew Garrett <mjg59@srcf.ucam.org> |
drm/i915: Deobfuscate the render p-state obfuscation
The ironlake render p-state support includes some rather odd variable
names. Clean them up in order to improve the readability of the code.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| f97108d1d0facc7902134ebc453b226bbd4d1cdb |
|
29-Jan-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add dynamic performance control support for Ironlake
Ironlake (and 965GM, which this patch doesn't support) supports a
hardware performance and power management feature that allows it to
adjust to changes in GPU load over time with software help. The goal
if this is to maximize performance/power for a given workload.
This patch enables that feature, which is also a requirement for
supporting Intelligent Power Sharing, a feature which allows for
dynamic budgeting of power between the CPU and GPU in Arrandale
platforms.
Tested-by: ykzhao <yakui.zhao@intel.com>
[anholt: Resolved against the irq handler loop removal]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| c4804411691bdd7d8a57e942cbb502fd52a90074 |
|
17-Dec-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Keep MCHBAR always enabled
As we need more and more controls within MCHBAR for memory config and
power management, this trys to keep MCHBAR enabled from driver load and
only tear down in driver unload.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 99fcb766a3a50466fe31d743260a3400c1aee855 |
|
07-Feb-2010 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: Update write_domains on active list after flush.
Before changing the status of a buffer with a pending write we will await
upon a new flush for that buffer. So we can take advantage of any flushes
posted whilst the buffer is active and pending processing by the GPU, by
clearing its write_domain and updating its last_rendering_seqno -- thus
saving a potential flush in deep queues and improves flushing behaviour
upon eviction for both GTT space and fences.
In order to reduce the time spent searching the active list for matching
write_domains, we move those to a separate list whose elements are
the buffers belong to the active/flushing list with pending writes.
Orignal patch by Chris Wilson <chris@chris-wilson.co.uk>, forward-ported
by me.
In addition to better performance, this also fixes a real bug. Before
this changes, i915_gem_evict_everything didn't work as advertised. When
the gpu was actually busy and processing request, the flush and subsequent
wait would not move active and dirty buffers to the inactive list, but
just to the flushing list. Which triggered the BUG_ON at the end of this
function. With the more tight dirty buffer tracking, all currently busy and
dirty buffers get moved to the inactive list by one i915_gem_flush operation.
I've left the BUG_ON I've used to prove this in there.
References:
Bug 25911 - 2.10.0 causes kernel oops and system hangs
http://bugs.freedesktop.org/show_bug.cgi?id=25911
Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops
within seconds after login
http://bugs.freedesktop.org/show_bug.cgi?id=26101
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Adam Lantos <hege@playma.org>
Cc: stable@kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4bdadb9785696439c6e2b3efe34aa76df1149c83 |
|
27-Jan-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Selectively enable self-reclaim
Having missed the ENOMEM return via i915_gem_fault(), there are probably
other paths that I also missed. By not enabling NORETRY by default these
paths can run the shrinker and take memory from the system (but not from
our own inactive lists because our shrinker can not run whilst we hold
the struct mutex) and this may allow the system to survive a little longer
whilst our drivers consume all available memory.
References:
OOM killer unexpectedly called with kernel 2.6.32
http://bugzilla.kernel.org/show_bug.cgi?id=14933
v2: Pass gfp into page mapping.
v3: Use new read_cache_page_gfp() instead of open-coding.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: Hugh Dickins <hugh.dickins@tiscali.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Eric Anholt <eric@anholt.net>
Cc: stable@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 500a8cc466a24e2fbc4c86ef9c6467ae2ffdeb0c |
|
13-Jan-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: parse eDP panel color depth from VBT block
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 33814341f22f13cec17e8d7fbf6f7e8000e3efa4 |
|
14-Jan-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: disable LVDS downclock by default
Many platform support this feature, and it can provide significant
power savings when the reduced refresh rate is low. However, on some
platforms a secondary (reduced) timing is provided but not actually
supported by the hardware. This results in undesirable flicker at
runtime.
So disable the feature by default, but allow users to opt-in to the
reduced clock behavior with a new module parameter, lvds_downclock,
that can be set to 1 to enable the feature.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b9241ea31fae4887104e5d1b3b18f4009c25a0c4 |
|
25-Nov-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Don't wait interruptible for possible plane buffer flush
When we setup buffer for display plane, we'll check any pending
required GPU flush and possible make interruptible wait for flush
complete. But that wait would be most possibly to fail in case of
signals received for X process, which will then fail modeset process
and put display engine in unconsistent state. The result could be
blank screen or CPU hang, and DDX driver would always turn on outputs
DPMS after whatever modeset fails or not.
So this one creates new helper for setup display plane buffer, and
when needing flush using uninterruptible wait for that.
This one should fix bug like https://bugs.freedesktop.org/show_bug.cgi?id=24009.
Also fixing mode switch stress test on Ironlake.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1d3c36ad4122651018599d4e3c9be0cccfbfb939 |
|
21-Dec-2009 |
Andrew Lutomirski <luto@mit.edu> |
drm/i915: Fix RC6 suspend/resume
We restored RC6 twice on resume, even with modesetting off. Instead,
only restore it once and skip RC6 initialization entirely in non-KMS mode.
Signed-off-by: Andy Lutomirski <luto@mit.edu>
Tested-by: Jeff Chua <jeff.chua.linux@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 76446cac68568fc7f5168a27deaf803ed22a4360 |
|
18-Dec-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: execbuf2 support
This patch adds a new execbuf ioctl, execbuf2, for use by clients that
want to control fence register allocation more finely. The buffer
passed in to the new ioctl includes a new relocation type to indicate
whether a given object needs a fence register assigned for the command
buffer in question.
Compatibility with the existing execbuf ioctl is implemented in terms
of the new code, preserving the assumption that fence registers are
required for pre-965 rendering commands.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: Remove pre-emptive clear_fence_reg()]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
[anholt: Removed dmesg spam]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b295d1b6e3e3f240d27cbe556d33ff5eb54721a7 |
|
16-Dec-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
drm/i915: Track whether cursor needs physical address in intel_device_info
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| cfdf1fa23f4074c9f8766dc67a928bbf680b1ac9 |
|
16-Dec-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
drm/i915: Implement IS_* macros using static tables
Instead of using the IS_I9XX etc macros that expand to a ton of
comparisons, use new struct intel_device_info to capture the
capabilities of the different chipsets. The drm_i915_private struct
will be initialized to point to the device info that correspond to
the actual device and this way, testing for a specific capability is
just a matter of checking a bit field.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| a2565377a5c31e25c77c7cabaf6752abe9a2d83a |
|
11-Dec-2009 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Update LVDS connector status when receiving ACPI LID event
Dirk reports that nothing is displayed on LVDS when using ubuntu 9.1 after
close/reopen the LID. And I also reproduce this issue on another laptop.
After some tests and debug, it seems that it is related with that the
LVDS status is not updated in time in course of suspend/resume.
Now the LID state is used to check whether the LVDS is connected or
disconnected. And when the LID is closed, it means that the LVDS is
disconnected. When it is reopened, it means that the LVDS is connected.
At the same time on some distributions the LID event is also used to put
the system into suspend state. When the LID is closed, the system will enter
the suspend state. When the LID is reopened, the system will be resumed.
In such case when the LID is closed, user-space script will receive the LID
notification event and detect the LVDS as disconnected. Then the system will
enter the suspended state. When the LID is reopened, the system will be
resumed. As the LVDS status is not updated in course of resume, it will cause
that the LVDS connector is marked as unused and disabled. After the resume is
finished,user-space script will try to configure the display mode for LVDS.
But unfortunately as the LVDS status is not updated in time and it is still
marked as disconnected, the LVDS and its corresponding CRTC will be disabled
again in the function of drm_helper_disable_unused_functions after changing
mode for LVDS.
So we had better check and update the status of LVDS connector after receiving
the LID notication event. Then after the system is resumed from suspended
state, we can set the display mode for LVDS correctly.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reported-by: Dirk Hohndel <hohndel@infradead.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: stable@kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0b5e8db639de032bd4febbb0a5b1cd2c19bac26d |
|
10-Dec-2009 |
Dave Airlie <airlied@redhat.com> |
Merge remote branch 'anholt/drm-intel-next' into drm-linus
Pull more Intel changes in, especially one to init the GTT properly
|
| 7e8b60faea972604c315634cff62d44803731ea9 |
|
08-Nov-2009 |
Andrew Lutomirski <luto@mit.edu> |
drm/i915: restore render clock gating on resume
Rather than restoring just a few clock gating registers on resume,
just reinitialize the whole thing.
Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Fixed up for RC6 support landed since the patch was written]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3ff99164f67aae78a2bd2313f65ad55bddb1ffea |
|
08-Dec-2009 |
Dave Airlie <airlied@redhat.com> |
Merge remote branch 'anholt/drm-intel-next' into drm-linus
This merges the upstream Intel tree and fixes up numerous conflicts
due to patches merged into Linus tree later in -rc cycle.
Conflicts:
drivers/char/agp/intel-agp.c
drivers/gpu/drm/drm_dp_i2c_helper.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_suspend.c
|
| f2b115e69d46344ae7afcaad5823496d2a0d8650 |
|
03-Dec-2009 |
Adam Jackson <ajax@redhat.com> |
drm/i915: Fix product names and #defines
IGD* isn't a useful name. Replace with the codenames, as sourced from
pci.ids.
Signed-off-by: Adam Jackson <ajax@redhat.com>
[anholt: Fixed up for merge with pineview/ironlake changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6b95a207c1fd552e7d017837c5eaf1b0173a48c9 |
|
18-Nov-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
drm/i915: Add intel implementation of the pageflip ioctl
Acked-by: Jakob Bornecrantz <jakob@vmware.com>
Acked-by: Thomas Hellström <thomas@shipmail.org>
Review-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jesse "Orange Smoothie" Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 103a196f4224dc6872081305cf7f82ebf67aa7bd |
|
27-Nov-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: PineView only has LVDS and CRT ports
PineView only has 2 ports for LVDS and CRT. Don't enable other
ports for it.
Cc: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6363ee6f496eb7e3b3f78dc105e522c7b496089b |
|
24-Nov-2009 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: parse child device from VBT
On some laptops there is no HDMI/DP. But the xrandr still reports
several disconnected HDMI/display ports. In such case the user will be
confused.
>DVI1 disconnected (normal left inverted right x axis y axis)
>DP1 disconnected (normal left inverted right x axis y axis)
>DVI2 disconnected (normal left inverted right x axis y axis)
>DP2 disconnected (normal left inverted right x axis y axis)
>DP3 disconnected (normal left inverted right x axis y axis)
This patch set is to use the child device parsed in VBT to decide whether
the HDMI/DP/LVDS/TV should be initialized.
Parse the child device from VBT.
The device class type is also added for LFP, TV, HDMI, DP output.
https://bugs.freedesktop.org/show_bug.cgi?id=22785
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 29874f44fbcbc24b231b42c9956f8f9de9407231 |
|
18-Nov-2009 |
Shaohua Li <shaohua.li@intel.com> |
drm/i915: fix gpio register detection logic for BIOS without VBT
if no VBT is present, crt_ddc_bus will be left at 0, and cause us
to use that for the GPIO register offset. That's never a valid register
offset, so let the "undefined" value be 0 instead of -1.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
[anholt: clarified the commit message a bit]
/drivers/gpu/drm/i915/i915_drv.h
|
| 18f9ed12f8c977e25d65a16af8e8d73f72417ba1 |
|
20-Nov-2009 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Enable LVDS downclock feature through EDID.
If more than one mode with the same resolution defined in EDID has different
refresh rate, it is thought that the downclock is found for LVDS.
We will program the different FPx0/1 register so that we can select dynamically
between the low and high frequency.
On the g4x platform we will use the CxSR feature to switch the different
refresh rate if the LVDS downclock feature is supported.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5586c8bc93ac5fe75f5fd14e8c7add5344d1c548 |
|
06-Nov-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Add more registers save/restore for Ironlake suspend
Add more display registers save/restore to fix unstable issues
during S4 testing on Ironlake. And DPLL_B_MD should not be restored
on Ironlake.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| c650156af34bffa3d3a62c9fe26eee595aab3fd1 |
|
03-Nov-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Add display hotplug event on Ironlake
Enable display hotplug irqs from Ibex Peak (PCH).
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 01c66889c14aa163c49355b3be2ccfb214500599 |
|
28-Oct-2009 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Add ACPI OpRegion support for Ironlake
Add the support of ACPI opregion on Ironlake so that the backlight
brightness can be adjusted by using ACPI interface
>/sys/class/backlight/acpi_video0/brightness
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Tested-by: Zhao Yakui <yakui.zhao@intel.com>
[zhenyuw: cleanups, fix typo for checking GSE irq and convert to
current irq handling logic.]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1df4b35b61df27fc5b173fe2789d976e40e1dc22 |
|
15-Sep-2009 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: kill i915_lp_ring_sync
It's not needed anymore.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5a5a0c64a99d7542c48c99d1a8bbb49e665842be |
|
15-Sep-2009 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: implement fastpath for overlay flip waiting
As long as the gpu can keep up, neither the cpu (waiting for gpu)
nore the gpu (waiting for vblank to do an overlay flip) stalls.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 02e792fbaadb75dec8e476a05b610e49908fc6a4 |
|
15-Sep-2009 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: implement drmmode overlay support v4
This implements intel overlay support for kms via a device-specific
ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on
dri-devel). We've reached the conclusion that such an infrastructure
only makes sense when multiple kms overlay implementations exists,
which atm don't (and it doesn't look like this is gonna change).
Open issues:
- Runs in sync with the gpu, i.e. unnecessary waiting. I've decided
to wait on this because the hw tends to hang when changing something
in this area. I left some dummy functions as infrastructure.
- polyphase filtering uses a static table.
- uses uninterruptible sleeps. Unfortunately the alternatives may
unnecessarily wedged the hw if/when we timeout too early (and
userspace only overloaded the batch buffers with stuff worth a few
secs of gpu time).
Changes since v1:
- fix off-by-one misconception on my side. This fixes fullscreen
playback.
Changes since v2:
- add underrun detection as spec'ed for i965.
- flush caches properly, fixing visual corruptions.
Changes since v4:
- fix up cache flushing of overlay memory regs.
- killed require_pipe_a logic - it hangs the chip.
Tested-By: diego.abelenda@gmail.com (on a 865G)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[anholt: Resolved against the MADVISE ioctl going in before this one]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| f0f8a9cecea322b215600d96cf0c1eb08343a4e9 |
|
15-Sep-2009 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: kill superflous IS_I855 macro
It is identical to I85X. Use that one instead.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[anholt: fix conflicts against the display function pointer stuff]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 48764bf43f746113fc77877d7e80f2df23ca4cbb |
|
15-Sep-2009 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/i915: add i915_lp_ring_sync helper
This just waits until the hw passed the current ring position with
cmd execution. This slightly changes the existing i915_wait_request
function to make uninterruptible waiting possible - no point in
returning to userspace while mucking around with the overlay, that
piece of hw is just too fragile.
Also replace a magic 0 with the symbolic constant (and kill the then
superflous comment) while I was looking at the code.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 97f5ab6651a996ecefed73e41684422f3b29d9a8 |
|
08-Oct-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add render standby support
Render standy allows the GPU to power down the render unit when idle.
In order for this to work, it needs a page of graphics memory to save
state. This patch allocates that page and enables the feature on
supported chipsets.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 91d3f9bacdb4950d2f79fe2ba296aa249f60d06c |
|
04-Nov-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Ironlake suspend/resume support
drm/i915: kill warning in intel_find_pll_g4x_dp
drm/i915: update watermarks before enabling PLLs
drm/i915: add FIFO watermark support for G4x
drm/i915: quiet DP i2c init
drm/i915: fix panel fitting filter coefficient select for Ironlake
drm/i915: fix to setup display reference clock control on Ironlake
drm/i915: Install a fence register for fbc on g4x
drm/i915: save/restore BLC histogram control reg across suspend/resume
drm/i915: Fix FDI M/N setting according with correct color depth
drm/i915: disable powersave feature for Ironlake currently
drm/i915: Fix render reclock availability detection.
drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
drm/i915: disable FBC for Pineview, fixing a boot hang.
|
| c9354c85c1c7bac788ce57d3c17f2016c1c45b1d |
|
02-Nov-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
i915: fix intel graphics suspend breakage due to resume/lid event confusion
In commit c1c7af60892070e4b82ad63bbfb95ae745056de0 ("drm/i915: force
mode set at lid open time") the intel graphics driver was taught to
restore the LVDS mode on lid open.
That caused problems with interaction with the suspend/resume code,
which commonly runs at the same time (suspend is often caused by the lid
close event, while lid open is commonly a resume event), which was
worked around with in commit 06891e27a9b5dba5268bb80e41a283f51335afe7
("drm/i915: fix suspend/resume breakage in lid notifier").
However, in the meantime the lid event code had also grown a user event
notifier (commit 06324194eee97a51b5f172270df49ec39192d6cc: "drm/i915:
generate a KMS uevent at lid open/close time"), and now _that_ causes
problems with suspend/resume and some versions of Xorg reacting to those
uevents by setting the mode.
So this effectively reverts that commit 06324194ee, and makes the lid
open protection logic against suspend/resume more explicit. This fixes
at least one laptop. See
http://bugzilla.kernel.org/show_bug.cgi?id=14484
for more details.
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 4204878179c99d419d392d78d817729992b4c442 |
|
21-Oct-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Ironlake suspend/resume support
This adds registers save/restore for Ironlake to make suspend work.
Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com>
[zhenyuw: some code re-orgnization, and add more save/restore for
FDI link and transcoder registers, also fix palette register for Ironlake]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0eb96d6ed38430b72897adde58f5477a6b71757a |
|
14-Oct-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: save/restore BLC histogram control reg across suspend/resume
Turns out some machines, like the ThinkPad X40 don't come back if you
don't save/restore this register.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| c03342fa6d4617a77cb867ee0ec71665d520eb69 |
|
29-Sep-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: disable powersave feature for Ironlake currently
Until we figure out the right setting for powersave features on
Ironlake, disable it for now. Also disable watermark update,
which has new registers for it on Ironlake too.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Resolved against the Pineview FBC changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 06027f9111b9f3244ddc40752428f7847b0b867e |
|
05-Oct-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
This hasn't fixed the regressions we were testing against, but clearly
should be required.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| a3e17eb8f4080a79738a938abe718be255247a44 |
|
10-Oct-2009 |
Zhao Yakui <yakui.zhao@intel.com> |
drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
According to the spec the LVDS_BORDER_ENABLE bit decides whether the border
data should be included in the active display and data sent to the panel.
Border should be used when in VGA centered (un-scaled) mode or when scaling
a 4:3 source image to a wide screen panel (typical 16:9).
So when the LVDS scaling is used, decide whether the LVDS_BORDER should be
enabled or not according to the current scaling mode.
At the same time fix the typo error in LVDS center scaling mode.
https://bugs.freedesktop.org/show_bug.cgi?id=23789
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
tested-by: Zhao Jian <jian.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9216d44dc13b5e858253f06d83ceea25a9b72f4f |
|
10-Oct-2009 |
Shaohua Li <shaohua.li@intel.com> |
drm/i915: disable FBC for Pineview, fixing a boot hang.
Pineview doesn't have this FBC mechanism, so this code doesn't apply.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9d34e5db07303c9609053e2e651aa6d1fc74e923 |
|
24-Sep-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Enable irq to trace batch buffer completion.
If we trigger a tracepoint for batch buffer submission, it is a reasonable
assumption that we wish to also trace the batch buffer completion. So in
order to capture the completion events, we need to enable irqs... However,
we cannot rely on the completion event to disable the irq later, so we
defer the irq disable to the retire request.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 94e0fb086fc5663c38bbc0fe86d698be8314f82f |
|
24-Sep-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (57 commits)
drm/i915: Handle ERESTARTSYS during page fault
drm/i915: Warn before mmaping a purgeable buffer.
drm/i915: Track purged state.
drm/i915: Remove eviction debug spam
drm/i915: Immediately discard any backing storage for uneeded objects
drm/i915: Do not mis-classify clean objects as purgeable
drm/i915: Whitespace correction for madv
drm/i915: BUG_ON page refleak during unbind
drm/i915: Search harder for a reusable object
drm/i915: Clean up evict from list.
drm/i915: Add tracepoints
drm/i915: framebuffer compression for GM45+
drm/i915: split display functions by chip type
drm/i915: Skip the sanity checks if the current relocation is valid
drm/i915: Check that the relocation points to within the target
drm/i915: correct FBC update when pipe base update occurs
drm/i915: blacklist Acer AspireOne lid status
ACPI: make ACPI button funcs no-ops if not built in
drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocks
drm/i915: intel_display.c handle latency variable efficiently
...
Fix up trivial conflicts in drivers/gpu/drm/i915/{i915_dma.c|i915_drv.h}
|
| 74dff282237ea8c0a5df1afd8526eac4b6cee063 |
|
15-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: framebuffer compression for GM45+
Add support for framebuffer compression on GM45 and above. Removes
some unnecessary I915_HAS_FBC checks as well (this is now part of the
FBC display function).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| e70236a8d3d0a4c100a0b9f7d394d9bda9c56aca |
|
21-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: split display functions by chip type
This patch splits out several of the display functions into a separate
display function table to avoid tons of chipset specific if..else
if..else if blocks all over. There are more opportunities for this
(some noted in the structure defintition); so more cleanup patches will
follow.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 28d520433b6375740990ab99d69b0d0067fd656b |
|
21-Sep-2009 |
Dave Airlie <airlied@redhat.com> |
drm/vgaarb: add VGA arbitration support to the drm and kms.
VGA arb requires DRM support for non-kms drivers, to turn on/off
irqs when disabling the mem/io regions.
VGA arb requires KMS support for GPUs where we can turn off VGA
decoding. Currently we know how to do this for intel and radeon
kms drivers, which allows them to be removed from the arbiter.
This patch comes from Fedora rawhide kernel.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3ef94daae7530b4ebcd2e5f48f1028cd2d2470ba |
|
14-Sep-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Add ioctl to set 'purgeability' of objects
Similar to the madvise() concept, the application may wish to mark some
data as volatile. That is in the event of memory pressure the kernel is
free to discard such buffers safe in the knowledge that the application
can recreate them on demand, and is simply using these as a cache.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 31169714fc928aed4e945b959dca2bedd259b9c9 |
|
14-Sep-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Register a shrinker to free inactive lists under memory pressure
This should help GEM handle memory pressure sitatuions more gracefully.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| e67b8ce1b59006ba41245838db60b6fcda365ba8 |
|
14-Sep-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Remove stored gtt_alignment
There is no need to store the gtt_alignment as it is either explicitly
set according to the hardware requirements (e.g. scanout) or the
minimum alignment is computed on demand.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| c1a1cdc159e211f045290f61ac95092e9708f5bc |
|
17-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: fix startup hang on some non-mobile platforms
Due to a bogus FBC support check and failing to check for FBC support
in the right places, mode setting on non-mobile platforms could fail
and hang in the FBC disable routine. Fix it up.
This fix highlights the need for cleanups in this area (function
pointers and better feature support checks). Patches for that to
follow.
Tested-by: Kenny Graunke <kenny@whitecape.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 06891e27a9b5dba5268bb80e41a283f51335afe7 |
|
14-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: fix suspend/resume breakage in lid notifier
We now unconditionally restore the mode at lid open time since some
platforms turn off the panel, pipes or other display elements when the
lid is closed. There's a problem with doing this at resume time
however.
At resume time, we'll get a lid event, but restoring the mode at that
time may not be safe (e.g. if we get the lid event before global state
has been restored), so check the suspended state and make sure our
restore is locked against other mode updates.
Tested-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| ba1234d17b3b1fe7087defb191a3c705f208aca6 |
|
14-Sep-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: Make dev_priv->mm.wedged an atomic_t
There is a very real possibility that multiple CPUs will notice that the
GPU is wedged. This introduces all sorts of potential race conditions.
Make the wedged flag atomic to mitigate this risk.
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 11ed50ec2a316928c2bacc1149bded86c6a96068 |
|
14-Sep-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: Implement GPU reset on i965
This patch puts in place the machinery to attempt to reset the GPU. This
will be used when attempting to recover from a GPU hang.
Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| f65d94211e2bcba17faf05a6a3809af0e4217767 |
|
14-Sep-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: Add hangcheck timer
We set a periodic timer to check on the GPU, resetting it every time a
batch is completed. If the timer elapses, we check acthd. If acthd
hasn't changed in two timer periods, we assume the chip is wedged.
This is implemented in such a way that it leaves the option open to
employ adaptive timer intervals in the future. One could wait until
several timer periods have elapsed before declaring the chip dead. If
the chip comes back after several periods but before the "dead"
threshold, the timer interval or dead threshold could be raised.
It is important to note that while checking for active requests, we need
to account for the fact that requests are removed from the list (i.e.
retired) in a deferred work queue handler. This means that merely
checking for an empty request_list is insufficient; the list could be
non-empty yet the GPU still idle, causing the hangcheck timer to
incorrectly mark the GPU as wedged (it took me a while to figure that
out---sigh...)
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 22be172423b0007a02a06d70db8aeb4d9e64c6b3 |
|
14-Sep-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: make i915_seqno_passed non-static
We'll need it in i915_irq.c for checking whether there are outstanding
requests. Also, the function really ought to return a bool, not an int.
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1341d655ddea37f307736af7030a3ef7c5648c31 |
|
14-Sep-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: Refactor save/restore code
We move the display-specific code into it's own functions, called
from the general GPU state save/restore functions. This will be needed
later by the GPU reset code.
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8082400327d8d2ca54254b593644942bed0edd25 |
|
11-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: framebuffer compression for pre-GM45
This patch adds framebuffer compression (good for about ~0.5W power
savings in the best case) support for pre-GM45 chips. GM45+ have a new,
more flexible FBC scheme that will be added in a separate patch.
FBC can't always be enabled: the compressed buffer must be physically
contiguous and reside in stolen space. So if you have a large display
and a small amount of stolen memory, you may not be able to take
advantage of FBC. In some cases, a BIOS setting controls how much
stolen space is available. Increasing this to 8 or 16M can help.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| c1c7af60892070e4b82ad63bbfb95ae745056de0 |
|
11-Sep-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: force mode set at lid open time
Some laptop platforms will disable pipes and/or planes at lid close time
and not restore them when the lid is opened again. So catch the lid
event, and if the lid was opened, force a mode restore.
Fixes fdo bug #21230.
Acked-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| af729a26ccc3ff9ad834a5e96f455aab20f176cd |
|
25-Aug-2009 |
Li Peng <peng.li@intel.com> |
Add G33 series in VGA hotplug support category
Test on the IGD chip, which is a G33-like graphic device.
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7839c5d5519b6d9e2ccf3cdbf1c39e3817ad0835 |
|
07-Sep-2009 |
Fabian Henze <hoacha@quantentunnel.de> |
drm/i915: add B43 chipset support
Signed-off-by: Fabian Henze <hoacha@quantentunnel.de>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| ec2a4c3fdc8e82fe82a25d800e85c1ea06b74372 |
|
04-Aug-2009 |
Dave Airlie <airlied@redhat.com> |
drm/i915: get the bridge device once.
The driver gets the bridge device in a number of places, upcoming
vga arb code paths need the bridge device, however they need it in
under a lock, and the pci lookup can allocate memory. So clean
this code up before then and get the bridge once for the driver lifetime.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0ef82af7253c1929a3995f271b8b0db462d1a0c3 |
|
05-Sep-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Pad ringbuffer with NOOPs before wrapping
According to the docs, the ringbuffer is not allowed to wrap in the middle
of an instruction.
G45 PRM, Vol 1b, p101:
While the “free space” wrap may allow commands to be wrapped around the
end of the Ring Buffer, the wrap should only occur between commands.
Padding (with NOP) may be required to follow this restriction.
Do as commanded.
[Having seen bug reports where there is evidence of split commands, but
apparently the GPU has continued on merrily before a bizarre and untimely
death, this may or may not fix a few random hangs.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 652c393a3368af84359da37c45afc35a91144960 |
|
17-Aug-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add dynamic clock frequency control
There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.
Signed-off-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 27c202ad7f141d4efa9c64e30bf4a4d3bcd799ae |
|
02-Jul-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: Move i915_gem_debugfs.c to i915_debugfs.c
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
[anholt: hand-applied for conflicts]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| db54501900ad3665dd669f5708ecd04fc5aed495 |
|
29-Aug-2009 |
David Müller (ELSOFT AG) <d.mueller@elsoft.ch> |
drm/i915: Improve CRTDDC mapping by using VBT info
Use VBT information to determine which DDC bus to use for CRTDCC.
Fall back to GPIOA if VBT info is not available.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested on: 855 (David), and 945GM, 965GM, GM45, and G45 (anholt)
/drivers/gpu/drm/i915/i915_drv.h
|
| a09ba7faf75fa4b21980d81de8e5f3d5c0785ccf |
|
29-Aug-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Fix CPU-spinning hangs related to fence usage by using an LRU.
The lack of a proper LRU was partially worked around by taking the fence
from the object containing the oldest seqno. But if there are multiple
objects inactive, then they don't have seqnos and the first fence reg
among them would be chosen. If you were trying to copy data between two
mappings, this could result in each page fault stealing the fence from
the other argument, and your application hanging.
https://bugs.freedesktop.org/show_bug.cgi?id=23566
https://bugs.freedesktop.org/show_bug.cgi?id=23220
https://bugs.freedesktop.org/show_bug.cgi?id=23253
https://bugs.freedesktop.org/show_bug.cgi?id=23366
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9c9fe1f841745184bbc5460c6f3909fded3b929b |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Use our own workqueue to avoid wedging the system along with the GPU.
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 32f9d658aee5be09ebdd28fc730630e61d0b46db |
|
23-Jul-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Add eDP support on IGDNG mobile chip
This adds embedded DisplayPort support on next mobile chip which
aims to replace origin LVDS port. VBT's driver feature block has
been used to determine the type of current internal panel for eDP
or LVDS.
Currently no panel fitting support for eDP and backlight control
would be added in future.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8a90523639f49dc4b4fa7ae47bb9c8ed73ea8577 |
|
11-Jul-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: refactor error detection & collection
This patch refactors the existing error detection and collection code,
placing most of it in i915_handle_error(). Additionally, we introduce a
work queue for scheduling post-crash tasks such as generating a uevent.
Using the uevent facility, userspace should be able to capture a
post-mortem dump for diagnostics.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| d05ca301997c94c2ef3c112b15319d13fa8cddab |
|
10-Jul-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Zap the GTT mapping when transitioning from untiled to tiled.
As of 52dc7d32b88156248167864f77a9026abe27b432, we could leave an old
linear GTT mapping in place, so that apps trying to GTT-mapped write in
tiled data wouldn't get the fence added, and garbage would get displayed.
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b5323599af68caa2da08b7041400b62049afb91e |
|
01-Jul-2009 |
Ben Gamari <bgamari.foss@gmail.com> |
drm/i915: Remove gtt_bound from drm_i915_gem_object
This wasn't even used as far as I could tell and will only confuse
people (like me).
Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 22bd50c5b9aaf46476cade52c4ae9afa21c44e15 |
|
06-Jul-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Don't update display FIFO watermark on IGDNG
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7662c8bd6545c12ac7b2b39e4554c3ba34789c50 |
|
26-Jun-2009 |
Shaohua Li <shaohua.li@intel.com> |
drm/i915: add FIFO watermark support
This patch from jbarnes and myself adds FIFO watermark control to the
driver. This is needed for both power saving features on new platforms
with the so-called "big FIFO" and for controlling FIFO allocation
between pipes in multi-head configurations.
It's also necessary infrastructure to support things like framebuffer
compression and configuration supportability checks (i.e. checking a
configuration against available bandwidth).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 63eeaf38251183ec2b1caee11e4a2c040cb5ce6c |
|
19-Jun-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: enable error detection & state collection
This patch enables error detection by enabling several types of error
interrupts. When an error interrupt is received, the interrupt
handler captures the error state; hopefully resulting in an accurate
set of error data (error type, active head pointer, etc.). The new
record is then available from sysfs. The current code will also dump
the error state to the system log.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| a4fc5ed69817c73e32571ad7837bb707f9890009 |
|
08-Apr-2009 |
Keith Packard <keithp@keithp.com> |
drm/i915: Add Display Port support
Signed-off-by: Keith Packard <keithp@keithp.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 52dc7d32b88156248167864f77a9026abe27b432 |
|
06-Jun-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Clear fence register on tiling stride change.
The fence register value also depends upon the stride of the object, so we
need to clear the fence if that is changed as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[anholt: Added 8xx and 965 paths, and renamed the confusing
i915_gem_object_tiling_ok function to i915_gem_object_fence_offset_ok]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8c4b8c3f34de4e2da20df042bba173fe557f8b45 |
|
17-Jun-2009 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/i915: Install fence register for tiled scanout on i915
With the work by Jesse Barnes to eliminate allocation of fences during
execbuffer, it becomes possible to write to the scan-out buffer with it
never acquiring a fence (simply by only ever writing to the object using
tiled GPU commands and never writing to it via the GTT). So for pre-i965
chipsets which require fenced access for tiled scan-out buffers, we need
to obtain a fence register.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 036a4a7d9272582fc7370359515d807393e2f728 |
|
08-Jun-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: handle interrupt on new chipset
Update interrupt handling methods for IGDNG with new registers
for display and graphics interrupt functions. As we won't use
irq-based vblank sync in dri2, so display interrupt on new chip
will be used for hotplug only in future.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| d765898970f35acef960581f678b9da9d5c779fa |
|
05-Jun-2009 |
Jesse Barnes <jbarnes at virtuousgeek.org> |
drm/i915: enable MCHBAR if needed
Using the new PNP resource checking code, this patch allows the i915
driver to allocate MCHBAR space if needed and use the BAR to determine
current memory settings.
[apw@canonical.com: moved to the new generic PNP resource interface]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
failure to update-index after git-am --reject to hand-apply
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9b9d172d06b0f2d51cc9431e2c6c3055f0cf10ef |
|
31-May-2009 |
yakui_zhao <yakui.zhao@intel.com> |
drm/i915: parse VBT general definition block to get the SDVO device info
The general definition block contains the child device tables, which include
the SDVO device info. For example: device slave address, device dvo port,
device type.
We will get the info of SDVO device by parsing the general definition blocks.
Only when a valid slave address is found, it is regarded as the SDVO device.
And the info of DVO port and slave address is recorded.
http://bugs.freedesktop.org/show_bug.cgi?id=20429
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 280da227c870a50f669de0c8d46bfb2c62da9995 |
|
05-Jun-2009 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
drm/i915: Add chipset/feature defines for for new chipsets
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
[anholt: dropped drm_pciids.h hunk to avoid loading an incomplete driver]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b962442e46a9340bdbc6711982c59ff0cc2b5afb |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Change GEM throttling to be 20ms like the comment says.
keithp didn't like the original 20ms plan because a cooperative client could
be starved by an uncooperative client. There may even have been problems
with cooperative clients versus cooperative clients. So keithp changed
throttle to just wait for the second to last seqno emitted by that client.
It worked well, until we started getting more round-trips to the server
due to DRI2 -- the server throttles in BlockHandler, and so if you did more
than one round trip after finishing your frame, you'd end up unintentionally
syncing to the swap.
Fix this by keeping track of the client's requests, so the client can wait
when it has an outstanding request over 20ms old. This should have
non-starving behavior, good behavior in the presence of restarts, and less
waiting. Improves high-settings openarena performance on my GM45 by 50%.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 1fd1c624362819ecc36db2458c6a972c48ae92d6 |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Save/restore cursor state on suspend/resume.
This may fix cursor corruption in X on resume, which would persist until
the cursor was hidden and then shown again.
V2: Also include the cursor control regs.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 8863170628da4b0b461eb96bf797df1dca0bd03e |
|
13-May-2009 |
Ma Ling <ling.ma@intel.com> |
drm/i915: Fetch SDVO LVDS mode lines from VBT, then reserve them
Signed-off-by: Ma Ling <ling.ma@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| c9ed4486bdee3b54cb544fc181057bc6bf1ae45c |
|
13-May-2009 |
Ma Ling <ling.ma@intel.com> |
drm/i915: Include 965GME pci ID in IS_I965GM(dev) to match UMS.
It fixed bug #21659
Signed-off-by: Ma Ling <ling.ma@intel.com>
[anholt: hand-applied because git-am is too picky]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 79f11c19a396e8cea7dad322dcfb46c0a8517fe6 |
|
30-Apr-2009 |
Keith Packard <keithp@keithp.com> |
drm/i915: save/restore fence registers across suspend/resume
This makes software fallbacks not do tiling wrong on i965 and later after
resume. It also should fix 945 performance reduction after resume which
would have disabled tiling without causing any visible effect.
Signed-off-by: Keith Packard <keithp@keithp.com>
[anholt: Fixed up the 915 case to not save/restore the new regs]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 049ef7e40fc9959db480b2753a1dbe734d98e948 |
|
30-Apr-2009 |
Keith Packard <keithp@keithp.com> |
drm/i915: x86 always has writeq. Add I915_READ64 for symmetry.
i386 has inline code for writeq and readq, so just use those instead of ugly
macros which evaluate arguments multiple times.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 72021788678523047161e97b3dfed695e802a5fd |
|
17-Nov-2008 |
Zhenyu Wang <zhenyu.z.wang@intel.com> |
drm/i915: add support for G41 chipset
This had been delayed for some time due to failure to work on the one piece
of G41 hardware we had, and lack of success reports from anybody else.
Current hardware appears to be OK.
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
[anholt: hand-applied due to conflicts with IGD patches]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3b1c1c1118880921da1188b7245e0470742802f8 |
|
01-Apr-2009 |
Matthew Garrett <mjg59@srcf.ucam.org> |
drm/i915: Unregister ACPI video driver when exiting
The i915 DRM triggers registration of the ACPI video driver on load. It
should unregister it at unload in order to avoid generating backtraces on
being reloaded.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b897e6fbc49dd84b2634bca664344d503b907ce9 |
|
14-Apr-2009 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: fix scheduling while holding the new active list spinlock
drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU.
drm/i915: Correctly set the write flag for get_user_pages in pread.
drm/i915: Fix use of uninitialized var in 40a5f0de
drm/i915: indicate framebuffer restore key in SysRq help message
drm/i915: sync hdmi detection by hdmi identifier with 2D
drm/i915: Fix a mismerge of the IGD patch (new .find_pll hooks missed)
drm/i915: Implement batch and ring buffer dumping
|
| 280b713b5b0fd84cf2469098aee88acbb5de859c |
|
13-Mar-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU.
Save the bit 17 state of the pages when freeing the page list, and
reswizzle them if necessary when rebinding the pages (in case they were
swapped out). Since we have userland with expectations that the swizzle
enums let it pread and pwrite contents accurately, we can't expose a new
swizzle enum for bit 17 (which it would have to GTT map to handle), so we
handle it down in pread and pwrite by swizzling the copy when bit 17 of the
page address is set.
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 6911a9b8ae8b2a1dab4dfda9c2bd20f7ca2961d6 |
|
02-Apr-2009 |
Ben Gamari <bgamari@gmail.com> |
drm/i915: Implement batch and ring buffer dumping
We create a debugfs node (i915_ringbuffer_data) to expose a hex dump
of the ring buffer itself. We also expose another debugfs node
(i915_ringbuffer_info) with information on the state (i.e. head, tail
addresses) of the ringbuffer.
For batchbuffer dumping, we look at the device's active_list, dumping
each object which has I915_GEM_DOMAIN_COMMAND in its read
domains. This is all exposed through the dri/i915_batchbuffers debugfs
file with a header for each object (giving the objects gtt_offset so
that it can be matched against the offset given in the
BATCH_BUFFER_START command.
Signed-off-by: Ben Gamari <bgamari@gmail.com>
Signed-off-by: Carl Worth <cworth@cworth.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 478c6a43fcbc6c11609f8cee7c7b57223907754f |
|
05-Apr-2009 |
Len Brown <len.brown@intel.com> |
Merge branch 'linus' into release
Conflicts:
arch/x86/kernel/cpu/cpufreq/longhaul.c
Signed-off-by: Len Brown <len.brown@intel.com>
|
| 5e118f4139feafe97e913df67b1f7c1e5083e535 |
|
20-Mar-2009 |
Carl Worth <cworth@cworth.org> |
drm/i915: Add a spinlock to protect the active_list
This is a baby-step in the direction of having finer-grained
locking than the struct_mutex. Specifically, this will enable
new debugging code to read the active list for printing out
GPU state when the GPU is wedged, (while the struct_mutex is
held, of course).
Signed-off-by: Carl Worth <cworth@cworth.org>
[anholt: indentation fix]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5ca58282089b11f64b911618036ee7676f12735b |
|
31-Mar-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add VGA hotplug support for 945+
Add VGA port hotplug detection to the i915 driver. When KMS is enabled,
plugging in or removing a VGA cable from the VGA connector will
generate a uevent, which indicates to userspace that it should re-probe
outputs on this device (to determine modes, etc.).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: dropped extra PORT_HOTPLUG_STAT clear with ack from jbarnes]
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 03ae61dd5701092aabb60a8cae9929dbf8dc25c6 |
|
28-Mar-2009 |
Len Brown <len.brown@intel.com> |
ACPI: fix CONFIG_ACPI=n build
drivers/gpu/drm/i915/i915_drv.c:102: error: too many arguments to
function ‘intel_opregion_init’
Signed-off-by: Len Brown <len.brown@intel.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 74a365b3f354fafc537efa5867deb7a9fadbfe27 |
|
19-Mar-2009 |
Matthew Garrett <mjg59@srcf.ucam.org> |
ACPI: Populate DIDL before registering ACPI video device on Intel
Intel graphics hardware that implements the ACPI IGD OpRegion spec
requires that the list of display devices be populated before any ACPI
video methods are called. Detect when this is the case and defer
registration until the opregion code calls it. Fixes crashes on HP
laptops.
http://bugzilla.kernel.org/show_bug.cgi?id=11259
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Len Brown <len.brown@intel.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2177832f2e20fceb32142bb4fd33ae68c8af8c5a |
|
23-Feb-2009 |
Shaohua Li <shaohua.li@intel.com> |
agp/intel: Add support for new intel chipset.
This is a G33-like desktop and mobile chipset.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 2017263e9e72974610179beaa85c4498b9c4b7a4 |
|
18-Feb-2009 |
Ben Gamari <bgamari@gmail.com> |
drm/i915: Convert i915 proc files to seq_file and move to debugfs.
Signed-off-by: Ben Gamari <bgamari@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 201361a54ed187d8595a283e3a4ddb213bc8323b |
|
11-Mar-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Fix lock order reversal with cliprects and cmdbuf in non-DRI2 paths.
This introduces allocation in the batch submission path that wasn't there
previously, but these are compatibility paths so we care about simplicity
more than performance.
kernel.org bug #12419.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Keith Packard <keithp@keithp.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 856fa1988ea483fc2dab84a16681dcfde821b740 |
|
19-Mar-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Make GEM object's page lists refcounted instead of get/free.
We've wanted this for a few consumers that touch the pages directly (such as
the following commit), which have been doing the refcounting outside of
get/put pages.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
/drivers/gpu/drm/i915/i915_drv.h
|
| 66824bd7b5dc22da367595359bfcd1149c4ce92a |
|
25-Feb-2009 |
Pierre Willenbrock <pierre@pirsoft.de> |
drm/i915: Don't restore palettes through VGA registers.
The VGA registers just hit the pipe registers that we already set through
MMIO. This fixes strange colors on resume.
Signed-off-by: Pierre Willenbrock <pierre@pirsoft.de>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| b70d11da61d751ad968c6f686d83ac1b0ae41466 |
|
03-Mar-2009 |
Kristian Høgsberg <krh@redhat.com> |
drm: Return EINVAL on duplicate objects in execbuffer object list
If userspace passes an object list with the same object appearing more
than once, we end up hitting the BUG_ON() in
i915_gem_object_set_to_gpu_domain() as it gets called a second time
for the same object.
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/drivers/gpu/drm/i915/i915_drv.h
|
| 5669fcacc58bf3a7386057addffd280d75380858 |
|
18-Feb-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: suspend/resume GEM when KMS is active
In the KMS case, we need to suspend/resume GEM as well. So on suspend, make
sure we idle GEM and stop any new rendering from coming in, and on resume,
re-init the framebuffer and clear the suspended flag.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 43565a0648e664744ac9201c199681451355edcc |
|
14-Feb-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
drm: Use spread spectrum when the bios tells us it's ok.
Lifted from the DDX modesetting.
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9880b7a527ffbb52f65c2de0a8d4eea86e24775e |
|
06-Feb-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add get_vblank_counter function for GM45
As discussed in the long thread about vblank related timeouts, it turns out
GM45 has different frame count registers than previous chips. This patch
adds support for them, which prevents us from waiting on really stale
sequence values in drm_wait_vblank (which rather than returning immediately
ends up timing out or getting interrupted).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0f973f27888e4664b253ab2cf69c67c2eb80ab1b |
|
27-Jan-2009 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add fence register management to execbuf
Adds code to set up fence registers at execbuf time on pre-965 chips as
necessary. Also fixes up a few bugs in the pre-965 tile register support
(get_order != ffs). The number of fences available to the kernel defaults
to the hw limit minus 3 (for legacy X front/back/depth), but a new parameter
allows userspace to override that as needed.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| ab657db12d7020629f26f30d287558a8d0e32b41 |
|
23-Jan-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Set up an MTRR covering the GTT at driver load.
We'd love to just be using PAT, but even on chips with PAT it gets disabled
sometimes due to an errata. It would probably be better to have pat_enabled
exported and only bother with this when !pat_enabled.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| 71acb5eb8d95b371f4cdd88a47f3c83c870d1c8f |
|
30-Dec-2008 |
Dave Airlie <airlied@linux.ie> |
drm/i915: add support for physical memory objects
This is an initial patch to do support for objects which needs physical
contiguous main ram, cursors and overlay registers on older chipsets.
These objects are bound on cursor bin, like pinning, and we copy
the data to/from the backing store object into the real one on attach/detach.
notes:
possible over the top in attach/detach operations.
no overlay support yet.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7d57382e65994ab7d01741373bd1c420370aed9f |
|
02-Jan-2009 |
Eric Anholt <eric@anholt.net> |
drm/i915: Add support for integrated HDMI on G4X hardware.
This is ported directly from the userland 2D driver code. The HDMI audio bits
aren't hooked up yet.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| 95281e352e19b670458563a5ca746195c183a98f |
|
18-Dec-2008 |
Hannes Eder <hannes@hanneseder.net> |
drm/i915: fix sparse warnings: declare one-bit bitfield as unsigned
Signed-off-by: Hannes Eder <hannes@hanneseder.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| 60fd99e3682c5acc74d58ed61dac93526d6976f7 |
|
04-Dec-2008 |
Eric Anholt <eric@anholt.net> |
drm/i915: Fix stolen memory detection on G45 and GM45.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 79e539453b34e35f39299a899d263b0a1f1670bd |
|
07-Nov-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| de151cf67ce52ed2d88083daa5e60c7858947329 |
|
12-Nov-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm/i915: add GEM GTT mapping support
Use the new core GEM object mapping code to allow GTT mapping of GEM
objects on i915. The fault handler will make sure a fence register is
allocated too, if the object in question is tiled.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7c1c2871a6a3a114853ec6836e9035ac1c0c7f7a |
|
28-Nov-2008 |
Dave Airlie <airlied@redhat.com> |
drm: move to kref per-master structures.
This is step one towards having multiple masters sharing a drm
device in order to get fast-user-switching to work.
It splits out the information associated with the drm master
into a separate kref counted structure, and allocates this when
a master opens the device node. It also allows the current master
to abdicate (say while VT switched), and a new master to take over
the hardware.
It moves the Intel and radeon drivers to using the sarea from
within the new master structures.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| ac5c4e76180a74c7f922f6fa71ace0cef45fa433 |
|
19-Dec-2008 |
Dave Airlie <airlied@redhat.com> |
drm/i915: GEM on PAE has problems - disable it for now.
On PAE systems, GEM allocates pages using shmem, and passes these
pages to be bound into AGP, however the AGP interfaces + the x86
set_memory interfaces all take unsigned long not dma_addr_t.
The initial fix for this was a mess, so we need to do this correctly
for 2.6.29.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| e47c68e9c5d71e2faab8c2b82f57c6c73e6456fd |
|
14-Nov-2008 |
Eric Anholt <eric@anholt.net> |
drm/i915: Make a single set-to-cpu-domain path and use it wherever needed.
This fixes several domain management bugs, including potential lack of cache
invalidation for pread, potential failure to wait for set_domain(CPU, 0),
and more, along with producing more intelligible code.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| ce44b0ea3dc04236d852d78a06f850d1f7b03f3d |
|
07-Nov-2008 |
Eric Anholt <eric@anholt.net> |
drm/i915: Move flushing list cleanup from flush request retire to request emit.
obj_priv->write_domain is "write domain if the GPU went idle now", not
"write domain at this moment." By postponing the clear, we confused the
concept, required more storage, and potentially emitted more flushes than
are required.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 461cba2d294fe83297edf8a6556912812903dce1 |
|
17-Nov-2008 |
Peng Li <peng.li@intel.com> |
drm/i915: Save/restore HWS_PGA on suspend/resume
It fixes suspend/resume failure of xf86-video-intel dri2
branch. As dri2 branch doesn't call I830DRIResume() to restore
hardware status page anymore, we need to preserve
this register across suspend/resume.
Signed-off-by: Peng Li <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 52440211dcdc52c0b757f8b34d122e11b12cdd50 |
|
18-Nov-2008 |
Keith Packard <keithp@keithp.com> |
drm: move drm vblank initialization/cleanup to driver load/unload
drm vblank initialization keeps track of the changes in driver-supplied
frame counts across vt switch and mode setting, but only if you let it by
not tearing down the drm vblank structure.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 7c463586427bbbad726ba561bae4ba5acada2481 |
|
04-Nov-2008 |
Keith Packard <keithp@keithp.com> |
drm/i915: Manage PIPESTAT to control vblank interrupts instead of IMR.
The pipestat fields affect reporting of all vblank-related interrupts, so we
have to reset them during the irq_handler, and while enabling vblank
interrupts. Otherwise, if a pipe status field had been set to non-zero
before enabling reporting, we would never see an interrupt again.
This patch adds i915_enable_pipestat and i915_disable_pipestat to abstract
out the steps needed to change the reported interrupts.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0baf823a10bd4131f70e9712d1f02de3c247f1df |
|
08-Nov-2008 |
Keith Packard <keithp@keithp.com> |
drm/i915: Move legacy breadcrumb out of the reserved status page area
Addresses in the hardware status page below index 0x20 are reserved for use
by the hardware. The legacy breadcrumb was sitting at index 5. Move it to
index 0x21, and make sure everyone uses the defined value instead of
hard-coded constants.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| bd95e0a4a6bb9485fe35dda62719663f6ceabae1 |
|
04-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i915: Remove racy delayed vblank swap ioctl.
When userland detected that this ioctl was supported (by version number check),
it used it in a racy way -- dispatch delayed swap, wait for vblank, continue
rendering. As there was no mechanism for it to wait for the swap to finish,
sometimes it would render before the swap and garbage would be displayed on
the screen.
By removing the ioctl and returning -EINVAL, userland returns to its previous,
correct rendering path of waiting for a vblank then dispatching a swap. The
only path that could have used this ioctl correctly was page flipping, which
relied on only one client running and emitting wait-for-vblank-before-rendering
in the command stream. That path also falls back correctly, at the performance
cost of not being able to queue up rendering before the flip occurs.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| 881ee9889c8b98671c5491e43666bf5d4f78a180 |
|
03-Nov-2008 |
Keith Packard <keithp@keithp.com> |
i915: Save/restore MCHBAR_RENDER_STANDBY on GM965/GM45
This register is set by the 2D driver to prevent lockups, and so it needs to
be preserved across suspend/resume too. This makes my X200s work.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
|
| da4a22cba7cb2d922691214aed6b1977f04efaff |
|
03-Nov-2008 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge branch 'io-mappings-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'io-mappings-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
io mapping: clean up #ifdefs
io mapping: improve documentation
i915: use io-mapping interfaces instead of a variety of mapping kludges
resources: add io-mapping functions to dynamically map large device apertures
x86: add iomap_atomic*()/iounmap_atomic() on 32-bit using fixmaps
|
| 5a125c3c79167e78ba44efef03af7090ef28eeaf |
|
23-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i915: Add GEM ioctl to get available aperture size.
This will let userland know when to submit its batchbuffers, before they get
too big to fit in the aperture.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0839ccb8ac6a9e2d5e175a4ae9c82b5c574d510d |
|
31-Oct-2008 |
Keith Packard <keithp@keithp.com> |
i915: use io-mapping interfaces instead of a variety of mapping kludges
Impact: optimize/clean-up the IO mapping implementation of the i915 DRM driver
Switch the i915 device aperture mapping to the io-mapping interface, taking
advantage of the cleaner API to extend it across all of the mapping uses,
including both pwrite and relocation updates.
This dramatically improves performance on 64-bit kernels which were using
the same slow path as 32-bit non-HIGHMEM kernels prior to this patch.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
/drivers/gpu/drm/i915/i915_drv.h
|
| 65e082c9a33a6e9f24e9a713a7d38d11206d3c3d |
|
24-Oct-2008 |
Len Brown <len.brown@intel.com> |
build fix: CONFIG_DRM_I915=y && CONFIG_ACPI=n
drivers/gpu/drm/i915/i915_opregion.c:340: error: implicit declaration of function ‘register_acpi_notifier’
drivers/gpu/drm/i915/i915_opregion.c:361: error: implicit declaration of function ‘unregister_acpi_notifier’
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 9e44af790f8bf8c3aa8a3101fd4f9bca2e932baa |
|
17-Oct-2008 |
Keith Packard <keithp@keithp.com> |
drm/i915: hold dev->struct_mutex and DRM lock during vblank ring operations
To synchronize clip lists with the X server, the DRM lock must be held while
looking at drawable clip lists. To synchronize with other ring access, the
ring mutex must be held while inserting commands into the ring. Failure to
do the first resulted in easy visual corruption when moving windows, and the
second could have corrupted the ring with DRI2.
Grabbing the DRM lock involves using the DRM tasklet mechanism, grabbing the
ring mutex means potentially sleeping. Deal with both of these by always
running the tasklet from a work handler.
Also, protect from clip list changes since the vblank request was queued by
making sure the window has at least one rectangle while looking inside,
preventing oopses .
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| ba1eb1d825fdef40f69871caf8e5842d00efbbc5 |
|
15-Oct-2008 |
Keith Packard <keithp@keithp.com> |
i915: Map status page cached for chips with GTT-based HWS location.
This should improve performance by avoiding uncached reads by the CPU (the
point of having a status page), and may improve stability. This patch only
affects G33, GM45 and G45 chips as those are the only ones using GTT-based
HWS mappings.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0cdad7e88a23910a911a3339ff2d70f8f952d7b8 |
|
15-Oct-2008 |
Keith Packard <keithp@keithp.com> |
i915: Use non-reserved status page index for breadcrumb
Dwords 0 through 0x1f are reserved for use by the hardware. Move the GEM
breadcrumb from 0x10 to 0x20 to keep out of this area.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 3043c60c485ad694392d3f71bd7ef9f5c5f7cfdd |
|
02-Oct-2008 |
Eric Anholt <eric@anholt.net> |
drm: Clean up many sparse warnings in i915.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 546b0974c39657017407c86fe79811100b60700d |
|
02-Sep-2008 |
Eric Anholt <eric@anholt.net> |
i915: Use struct_mutex to protect ring in GEM mode.
In the conversion for GEM, we had stopped using the hardware lock to protect
ring usage, since it was all internal to the DRM now. However, some paths
weren't converted to using struct_mutex to prevent multiple threads from
concurrently working on the ring, in particular between the vblank swap handler
and ioctls.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 673a394b1e3b69be886ff24abfd6df97c52e8d08 |
|
30-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm: Add GEM ("graphics execution manager") to i915 driver.
GEM allows the creation of persistent buffer objects accessible by the
graphics device through new ioctls for managing execution of commands on the
device. The userland API is almost entirely driver-specific to ensure that
any driver building on this model can easily map the interface to individual
driver requirements.
GEM is used by the 2d driver for managing its internal state allocations and
will be used for pixmap storage to reduce memory consumption and enable
zero-copy GLX_EXT_texture_from_pixmap, and in the 3d driver is used to enable
GL_EXT_framebuffer_object and GL_ARB_pixel_buffer_object.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| 0a3e67a4caac273a3bfc4ced3da364830b1ab241 |
|
30-Sep-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
drm: Rework vblank-wait handling to allow interrupt reduction.
Previously, drivers supporting vblank interrupt waits would run the interrupt
all the time, or all the time that any 3d client was running, preventing the
CPU from sleeping for long when the system was otherwise idle. Now, interrupts
are disabled any time that no client is waiting on a vblank event. The new
method uses vblank counters on the chipsets when the interrupts are turned
off, rather than counting interrupts, so that we can continue to present
accurate vblank numbers.
Co-author: Michel Dänzer <michel@tungstengraphics.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
|
| b9bfdfe6703eb089839d48316a79c84924a3c335 |
|
26-Aug-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
new chip name is GM45
Author: Zhenyu Wang <zhenyu.z.wang@intel.com>
i915: official name for GM45 chipset
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
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| 317c35d1446f68b34d4de4e1100fc01680bd4877 |
|
26-Aug-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
separate i915 suspend/resume functions into their own file
[Patch against drm-next. Consider this a trial balloon for our new Linux
development model.]
This is a big chunk of code. Separating it out makes it easier to change
without churn on the main i915_drv.c file (and there will be churn as we
fix bugs and add things like kernel mode setting). Also makes it easier
to share this file with BSD.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
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| 8ee1c3db9075cb3211352e737e0feb98fd733b20 |
|
05-Aug-2008 |
Matthew Garrett <mjg59@srcf.ucam.org> |
Add Intel ACPI IGD OpRegion support
This adds the support necessary for allowing ACPI backlight control to
work on some newer Intel-based graphics systems. Tested on Thinkpad T61
and HP 2510p hardware.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
/drivers/gpu/drm/i915/i915_drv.h
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| ed4cb4142b242d8090d3811d5eb4abf6aa985bc8 |
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29-Jul-2008 |
Eric Anholt <eric@anholt.net> |
i915: Add support for MSI and interrupt mitigation.
Previous attempts at interrupt mitigation had been foiled by i915_wait_irq's
failure to update the sarea seqno value when the status page indicated that
the seqno had already been passed. MSI support has been seen to cut CPU
costs by up to 40% in some workloads by avoiding other expensive interrupt
handlers for frequent graphics interrupts.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
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| 585fb111348f7cdc30c6a1b903987612ddeafb23 |
|
29-Jul-2008 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
i915: Use more consistent names for regs, and store them in a separate file.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
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| 0790d5e148c0747499742a3c09ba5f1c07f9ed0d |
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30-Jul-2008 |
Keith Packard <keithp@keithp.com> |
i915: remove settable use_mi_batchbuffer_start
The driver can know what hardware requires MI_BATCH_BUFFER vs
MI_BATCH_BUFFER_START; there's no reason to let user mode configure this.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
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| c0e09200dc0813972442e550a5905a132768e56c |
|
29-May-2008 |
Dave Airlie <airlied@redhat.com> |
drm: reorganise drm tree to be more future proof.
With the coming of kernel based modesetting and the memory manager stuff,
the everything in one directory approach was getting very ugly and
starting to be unmanageable.
This restructures the drm along the lines of other kernel components.
It creates a drivers/gpu/drm directory and moves the hw drivers into
subdirectores. It moves the includes into an include/drm, and
sets up the unifdef for the userspace headers we should be exporting.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/i915/i915_drv.h
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