| c1003d9c90f410777ab57f675b2a575c9c7ab5d7 |
|
24-May-2011 |
Francisco Jerez <currojerez@riseup.net> |
drm/nv17-nv40: Fix modesetting failure when pitch == 4096px (fdo bug 35901).
Reported-by: Mario Bachmann <grafgrimm77@gmx.de>
Tested-by: Greg Turner <gmturner007@ameritech.net>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 12fb9525075982bc65cfd71427dd7afdf47bafed |
|
19-Nov-2010 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau: introduce a util function to wait on reg != val
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 042206c0cd4924879c4292c5ffa2bf1e8023ae5a |
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21-Oct-2010 |
Francisco Jerez <currojerez@riseup.net> |
drm/nouveau: Implement the vblank DRM hooks.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 63f7fcfebd2ff1995b649101d6120b60fa0e5b06 |
|
22-Oct-2010 |
Francisco Jerez <currojerez@riseup.net> |
drm/nv04: Make CRTC base changes effective in the next hsync.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 5eb94fbba39e71f04d629f8197343273b56e25eb |
|
07-Oct-2010 |
Francisco Jerez <currojerez@riseup.net> |
drm/nv11: Fix bad PLL detection false positive.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 23357e4da0e1b39c9dfd64a1db0deafc6d70b554 |
|
28-Sep-2010 |
Francisco Jerez <currojerez@riseup.net> |
drm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 442b626ece6fbbe7f52c03a09f85ae5755f29eab |
|
16-Sep-2010 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nv04-nv40: import initial pm backend
Currently just hooked up to the already-existing nouveau_hw, which should
handle all relevant chipsets as well as we currently can.
This will likely be eventually split out and improved into chipset specific
code at a later point.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
|
| 855a95e4fc2ac6b758145ca7d6a0c95b66a57ef8 |
|
16-Sep-2010 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau: make the behaviour of get_pll_limits() consistent
This replaces all the pll_types definitions for ones that match the types
used in the tables in recent VBIOS versions.
get_pll_limits() will now accept either type or register value as input
across all limits table versions, and will store the actual register ID
that a PLL type refers to in the returned structure.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 4295f188e8297660b498e021caee430a40558d8b |
|
26-Aug-2010 |
Francisco Jerez <currojerez@riseup.net> |
drm/nv20: Use the nv30 CRTC bandwidth calculation code.
nv2x CRTC FIFOs are as large as in nv3x (4kB it seems), and the FIFO
control registers have the same layout: we can make them share the
same implementation.
Previously we were using the nv1x code, but the calculated FIFO
watermarks are usually too low for nv2x and they cause horrible
scanout artifacts. They've gone unnoticed until now because we've been
leaving one of the bandwidth regs uninitialized (CRE 47, which
contains the most significant bits of FFLWM), so everything seemed to
work fine except in some cases after a cold boot, depending on the
memory bandwidth and pixel clocks used.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
|
| 4a9f822fe1a6ca5de7d8cdd5efbead3b9ab4283b |
|
20-Jul-2010 |
Francisco Jerez <currojerez@riseup.net> |
drm/nv17-nv4x: Attempt to init some external TMDS transmitters.
sil164 and friends are the most common, usually they just need to be
poked once because a fixed configuration is enough for any modes and
clocks, so they worked without this patch if the BIOS had done a good
job on POST. Display couldn't survive a suspend/resume cycle though.
Unfortunately, BIOS scripts are useless here.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
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| 04a39c577f4114a3f098ee8ef0e20f7778b5ddad |
|
24-Feb-2010 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau: merge nvbios and nouveau_bios_info
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
|
| 6ee738610f41b59733f63718f0bdbcba7d3a3f12 |
|
11-Dec-2009 |
Ben Skeggs <bskeggs@redhat.com> |
drm/nouveau: Add DRM driver for NVIDIA GPUs
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA.
This driver is a KMS-based driver and requires a compatible nouveau
userspace libdrm and nouveau X.org driver.
This driver requires firmware files not available in this kernel tree,
interested parties can find them via the nouveau project git archive.
This driver is reverse engineered, and is in no way supported by nVidia.
Support for nearly the complete range of nvidia hw from nv04->g80 (nv50)
is available, and the kms driver should support driving nearly all
output types (displayport is under development still) along with supporting
suspend/resume.
This work is all from the upstream nouveau project found at
nouveau.freedesktop.org.
The original authors list from nouveau git tree is:
Anssi Hannula <anssi.hannula@iki.fi>
Ben Skeggs <bskeggs@redhat.com>
Francisco Jerez <currojerez@riseup.net>
Maarten Maathuis <madman2003@gmail.com>
Marcin Kościelnicki <koriakin@0x04.net>
Matthew Garrett <mjg@redhat.com>
Matt Parnell <mparnell@gmail.com>
Patrice Mandin <patmandin@gmail.com>
Pekka Paalanen <pq@iki.fi>
Xavier Chantry <shiningxc@gmail.com>
along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/nouveau/nouveau_hw.c
|