| 7b76e479e0f9d2f106bdf0686eff075837a6429a |
|
20-Mar-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: cayman gpu init updates for trinity
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 86a4d69c0ad62ced87a74bbd43f2acefc66a97b0 |
|
01-Feb-2012 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon/kms: common definitions for blit copy code
R600/700 and Evergreen/NI blit code have a few redundant
definitions in respective .c file. Move common definitions
into a separate (new) .h file.
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| e32eb50dbe43862606a51caa94368ec6bd019434 |
|
23-Oct-2011 |
Christian König <deathsimple@vodafone.de> |
drm/radeon: rename struct radeon_cp to radeon_ring
That naming seems to make more sense, since we not
only want to run PM4 rings with it.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| bf85279958da96cb4b11aac89b34f0424c3c120e |
|
13-Oct-2011 |
Christian König <deathsimple@vodafone.de> |
drm/radeon: make cp variable an array
Replace cp, cp1 and cp2 members with just an array
of radeon_cp structs.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 7b1f2485db253aaa0081e1c5213533e166130732 |
|
23-Sep-2011 |
Christian König <deathsimple@vodafone.de> |
drm/radeon: make all functions work with multiple rings.
Give all asic and radeon_ring_* functions a
radeon_cp parameter, so they know the ring to work with.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 77b1bad423599c9841ea282a82172f039bb2ff92 |
|
26-Oct-2011 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: flush read cache for gtt with fence on r6xx and newer GPU V3
Cayman seems to be particularly sensitive to read cache returning
old data after bind/unbind to GTT. Flush read cache for GTT range
with each fences for all new hw. Should fix several rendering glitches.
Like
V2 flush whole address space
V3 also flush shader read cache
https://bugs.freedesktop.org/show_bug.cgi?id=40221
https://bugs.freedesktop.org/show_bug.cgi?id=38022
https://bugzilla.redhat.com/show_bug.cgi?id=738790
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 06c9c2332cc3bffcc184f32ee503dc0a4eb83de0 |
|
24-Oct-2011 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms/cayman/blit: specify CP_COHER_CNTL2 with surface_sync
CP_COHER_CNTL2 has to be programmed manually when submitting packets
to the ring directly rather than programmed via an IB.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 9bb7703c5ea62ca1925cbfa0cd776f04de96fcf2 |
|
22-Oct-2011 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: rework texture cache flush in r6xx+ blit code
Move the TC flush before the texture setup to match mesa and
the ddx. Also, move the TC flush into the texture setup
function.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| fb3d9e97e1ad5f2c19b68fe5a0c6a95bf57c65c3 |
|
13-Oct-2011 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon/kms: blit code commoning
factor out most of evergreen blit code and use the refactored code
from r600 that is now common for both r600 and evergreen
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 6018faf58da5be0f0307b7bd2af113b9a60b7a7e |
|
13-Oct-2011 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon/kms: demystify evergreen blit code
some bits in 3D registers used by blit functions look like
magic and this is hard to follow; change them to a little bit
more meaningful pre-defined constants
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| eb32d0c34e64666b5f9d9c040ac85d96ecd1e6ee |
|
13-Oct-2011 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon/kms: simplify evergreen blit code
Covert 4k pages to multiples of 64x64x4 tiles.
This is also more efficient than a scanline based
approach from the MC's perspective.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| cbdd45015af78ec9e75ed7a3df8b76048c4d289f |
|
14-Oct-2011 |
Andi Kleen <ak@linux.intel.com> |
drm/radeon: Remove more bogus inlines in the radeon driver.
Remove bogus inlines in evergreen and r100.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| c61d0af9131976db150c40996a71387ba59edb67 |
|
12-Jul-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms/evergreen: emit SQ_LDS_RESOURCE_MGMT for blits
Compute drivers may change this, so make sure to emit it to
avoid errors in bo blits.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=39119
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| d5c5a72f2a5821ba3ebdbe02bce03345790458aa |
|
31-May-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add support for Llano Fusion APUs
- add gpu init support
- add blit support
- add ucode loader
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| cb92d452ba665205ad6bfb424c0ef009cf26587d |
|
25-May-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add blit support for cayman (v2)
Allows us to use the 3D engine for memory management
and allows us to use vram beyond the BAR aperture.
v2: fix copy paste typo
Reported-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| ac10f81d94f49f1bd9618680263400d275ddf825 |
|
25-May-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms/blit: workaround some hw issues on evergreen+
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 38f1cff0863809587b5fd10ecd0c24c8b543a48c |
|
16-Mar-2011 |
Dave Airlie <airlied@redhat.com> |
Merge commit '5359533801e3dd3abca5b7d3d985b0b33fd9fe8b' into drm-core-next
This commit changed an internal radeon structure, that meant a new driver
in -next had to be fixed up, merge in the commit and fix up the driver.
Also fixes a trivial nouveau merge.
Conflicts:
drivers/gpu/drm/nouveau/nouveau_mem.c
|
| 34db18abd376b2075c760c38f0b861aed379415d |
|
14-Mar-2011 |
Dave Airlie <airlied@redhat.com> |
Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-next
* 'intel/drm-intel-next' of ../drm-next: (755 commits)
drm/i915: Only wait on a pending flip if we intend to write to the buffer
drm/i915/dp: Sanity check eDP existence
drm/i915: Rebind the buffer if its alignment constraints changes with tiling
drm/i915: Disable GPU semaphores by default
drm/i915: Do not overflow the MMADDR write FIFO
Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing"
drm/i915: Don't save/restore hardware status page address register
drm/i915: don't store the reg value for HWS_PGA
drm/i915: fix memory corruption with GM965 and >4GB RAM
Linux 2.6.38-rc7
Revert "TPM: Long default timeout fix"
drm/i915: Re-enable GPU semaphores for SandyBridge mobile
drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"
Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU"
drm/i915: Allow relocation deltas outside of target bo
drm/i915: Silence an innocuous compiler warning for an unused variable
fs/block_dev.c: fix new kernel-doc warning
ACPI: Fix build for CONFIG_NET unset
mm: <asm-generic/pgtable.h> must include <linux/mm_types.h>
x86: Use u32 instead of long to set reset vector back to 0
...
Conflicts:
drivers/gpu/drm/i915/i915_gem.c
|
| 5359533801e3dd3abca5b7d3d985b0b33fd9fe8b |
|
14-Mar-2011 |
Dave Airlie <airlied@redhat.com> |
drm/radeon: fix problem with changing active VRAM size. (v2)
So we used to use lpfn directly to restrict VRAM when we couldn't
access the unmappable area, however this was removed in
93225b0d7bc030f4a93165347a65893685822d70 as it also restricted
the gtt placements. However it was only later noticed that this
broke on some hw.
This removes the active_vram_size, and just explicitly sets it
when it changes, TTM/drm_mm will always use the real_vram_size,
and the active vram size will change the TTM size used for lpfn
setting.
We should re-work the fpfn/lpfn to per-placement at some point
I suspect, but that is too late for this kernel.
Hopefully this addresses:
https://bugs.freedesktop.org/show_bug.cgi?id=35254
v2: fix reported useful VRAM size to userspace to be correct.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 441921d5309cfe098747d9840fd71bdc6ca2a93b |
|
18-Feb-2011 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/radeon: embed struct drm_gem_object
Unconditionally initialize the drm gem object - it's not
worth the trouble not to for the few kernel objects.
This patch only changes the place of the drm gem object,
access is still done via pointers.
v2: Uncoditionally align the size in radeon_bo_create. At
least the r600/evergreen blit code didn't to this, angering
the paranoid gem code.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 27dcfc102279867ef0080d3b27e0f8306cac53d1 |
|
10-Feb-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: use linear aligned for evergreen/ni bo blits
Not only is linear aligned supposedly more performant,
linear general is only supported by the CB in single
slice mode. The texture hardware doesn't support
linear general, but I think the hw automatically
upgrades it to linear aligned.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 0f234f5fdca1e31c7a6333c3633edc653cf3e598 |
|
14-Feb-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: evergreen/ni big endian fixes (v2)
Based on 6xx/7xx endian fixes from Cédric Cano.
v2: fix typo in shader
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 129205910f882e25c728e0e415743f8451a4c470 |
|
02-Feb-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add updated ib_execute function for evergreen
Adds new packet to disable DX9 constant emulation.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 1e644d6dce366a7bae22484f60133b61ba322911 |
|
27-Jan-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: re-emit full context state for evergreen blits
clear state doesn't seem to work properly in some cases
Fixes hangs in heavy 3D on some evergreen cards reported on
IRC.
May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=33381
possibly others.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@gmail.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| ff5b8562d965687261968d02762f9ae73e80a948 |
|
07-Jan-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add bo blit support for NI
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| e719ebd916c2ecee072affc9e7f0b92aa33c2f94 |
|
22-Nov-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add bo blit support for Ontario fusion APUs
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 268b2510de14f62134d87ba9b4981816192db386 |
|
18-Nov-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: fix alignment when allocating buffers
We were previously dropping alignment requests on the floor
when allocating buffers so we always ended up page aligned.
Certain tiling modes on 6xx+ require larger alignment which
wasn't happening before.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: Jerome Glisse <j.glisse@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 7e94250312d8b32a18e7e96cee19f2795d224e8c |
|
19-Oct-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: enable unmappable vram for evergreen
Evergreen now has blit support, but unmappable vram support
was disabled in c919b371cb734f42b1130e706ecee262f8d9261d
(drm/radeon/kms: avoid corner case issue with unmappable vram V2)
due to merge ordering. This re-enables unmappable vram on
evergreen.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 2281a378e1830d7ab78d3067f228e4e55d368b0d |
|
21-Oct-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms/evergreen: set the clear state to the blit state
The hw stores a default clear state for registers in the context
range that can be initialized when the CP is set up. Set the
blit state as the default clear state and use the CLEAR_STATE
packet to load the blit state rather than loading it from an IB.
This reduces overhead when doing bo moves using the 3D engine.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| 2126d0a4a205e2d6b763434f892524cd60f74228 |
|
06-Oct-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: make sure blit addr masks are 64 bit
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|
| d7ccd8fc11700502b5a104b7bad595b492a3aa1b |
|
09-Sep-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add drm blit support for evergreen
This patch implements blit support for bo moves using
the 3D engine. It uses the same method as r6xx/r7xx:
- store the base state in an IB
- emit variable state and vertex buffers to do the blit
This allows the hw to move bos using the 3D engine and allows
full use of vram beyond the pci aperture size.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/drivers/gpu/drm/radeon/evergreen_blit_kms.c
|