Cross Reference: /drivers/net/ethernet/mellanox/mlx4/cmd.c

Lines Matching refs:mfunc
178 	u32 status = readl(&priv->mfunc.comm->slave_read);
191 		     &priv->mfunc.comm->slave_write);
371 	struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
1090 	struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1107 		ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1108 				      priv->mfunc.master.slave_state[slave].vhcr_dma,
1230 		ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1231 				      priv->mfunc.master.slave_state[slave].vhcr_dma,
1239 			 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1255 	struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1300 		priv->mfunc.master.slave_state[slave].cookie = 0;
1301 		mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1336 	spin_lock(&priv->mfunc.master.slave_state_lock);
1341 	spin_unlock(&priv->mfunc.master.slave_state_lock);
1349 		     &priv->mfunc.comm[slave].slave_read);
1357 	spin_lock(&priv->mfunc.master.slave_state_lock);
1360 	spin_unlock(&priv->mfunc.master.slave_state_lock);
1366 		     &priv->mfunc.comm[slave].slave_read);
1377 	struct mlx4_mfunc *mfunc =
1380 		container_of(mfunc, struct mlx4_priv, mfunc);
1400 					  &mfunc->comm[slave].slave_write));
1401 			slt = swab32(readl(&mfunc->comm[slave].slave_read))
1438 	wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1442 		rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1458 	__raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1459 	__raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1471 	priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1472 					    &priv->mfunc.vhcr_dma,
1474 	if (!priv->mfunc.vhcr) {
1480 		priv->mfunc.comm =
1484 		priv->mfunc.comm =
1487 	if (!priv->mfunc.comm) {
1493 		priv->mfunc.master.slave_state =
1496 		if (!priv->mfunc.master.slave_state)
1500 			s_state = &priv->mfunc.master.slave_state[i];
1505 				     &priv->mfunc.comm[i].slave_write);
1507 				     &priv->mfunc.comm[i].slave_read);
1523 		memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
1524 		priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1525 		INIT_WORK(&priv->mfunc.master.comm_work,
1527 		INIT_WORK(&priv->mfunc.master.slave_event_work,
1529 		INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1531 		spin_lock_init(&priv->mfunc.master.slave_state_lock);
1532 		priv->mfunc.master.comm_wq =
1534 		if (!priv->mfunc.master.comm_wq)
1562 	flush_workqueue(priv->mfunc.master.comm_wq);
1563 	destroy_workqueue(priv->mfunc.master.comm_wq);
1567 			kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1569 	kfree(priv->mfunc.master.slave_state);
1571 	iounmap(priv->mfunc.comm);
1574 					     priv->mfunc.vhcr,
1575 					     priv->mfunc.vhcr_dma);
1576 	priv->mfunc.vhcr = NULL;
1590 	priv->mfunc.vhcr = NULL;
1621 		flush_workqueue(priv->mfunc.master.comm_wq);
1622 		destroy_workqueue(priv->mfunc.master.comm_wq);
1625 				kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1627 		kfree(priv->mfunc.master.slave_state);
1630 	iounmap(priv->mfunc.comm);
1632 		     priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1633 	priv->mfunc.vhcr = NULL;