1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#include <linux/sched.h> 36#include <linux/slab.h> 37#include <linux/export.h> 38#include <linux/pci.h> 39#include <linux/errno.h> 40 41#include <linux/mlx4/cmd.h> 42#include <linux/semaphore.h> 43 44#include <asm/io.h> 45 46#include "mlx4.h" 47#include "fw.h" 48 49#define CMD_POLL_TOKEN 0xffff 50#define INBOX_MASK 0xffffffffffffff00ULL 51 52#define CMD_CHAN_VER 1 53#define CMD_CHAN_IF_REV 1 54 55enum { 56 /* command completed successfully: */ 57 CMD_STAT_OK = 0x00, 58 /* Internal error (such as a bus error) occurred while processing command: */ 59 CMD_STAT_INTERNAL_ERR = 0x01, 60 /* Operation/command not supported or opcode modifier not supported: */ 61 CMD_STAT_BAD_OP = 0x02, 62 /* Parameter not supported or parameter out of range: */ 63 CMD_STAT_BAD_PARAM = 0x03, 64 /* System not enabled or bad system state: */ 65 CMD_STAT_BAD_SYS_STATE = 0x04, 66 /* Attempt to access reserved or unallocaterd resource: */ 67 CMD_STAT_BAD_RESOURCE = 0x05, 68 /* Requested resource is currently executing a command, or is otherwise busy: */ 69 CMD_STAT_RESOURCE_BUSY = 0x06, 70 /* Required capability exceeds device limits: */ 71 CMD_STAT_EXCEED_LIM = 0x08, 72 /* Resource is not in the appropriate state or ownership: */ 73 CMD_STAT_BAD_RES_STATE = 0x09, 74 /* Index out of range: */ 75 CMD_STAT_BAD_INDEX = 0x0a, 76 /* FW image corrupted: */ 77 CMD_STAT_BAD_NVMEM = 0x0b, 78 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */ 79 CMD_STAT_ICM_ERROR = 0x0c, 80 /* Attempt to modify a QP/EE which is not in the presumed state: */ 81 CMD_STAT_BAD_QP_STATE = 0x10, 82 /* Bad segment parameters (Address/Size): */ 83 CMD_STAT_BAD_SEG_PARAM = 0x20, 84 /* Memory Region has Memory Windows bound to: */ 85 CMD_STAT_REG_BOUND = 0x21, 86 /* HCA local attached memory not present: */ 87 CMD_STAT_LAM_NOT_PRE = 0x22, 88 /* Bad management packet (silently discarded): */ 89 CMD_STAT_BAD_PKT = 0x30, 90 /* More outstanding CQEs in CQ than new CQ size: */ 91 CMD_STAT_BAD_SIZE = 0x40, 92 /* Multi Function device support required: */ 93 CMD_STAT_MULTI_FUNC_REQ = 0x50, 94}; 95 96enum { 97 HCR_IN_PARAM_OFFSET = 0x00, 98 HCR_IN_MODIFIER_OFFSET = 0x08, 99 HCR_OUT_PARAM_OFFSET = 0x0c, 100 HCR_TOKEN_OFFSET = 0x14, 101 HCR_STATUS_OFFSET = 0x18, 102 103 HCR_OPMOD_SHIFT = 12, 104 HCR_T_BIT = 21, 105 HCR_E_BIT = 22, 106 HCR_GO_BIT = 23 107}; 108 109enum { 110 GO_BIT_TIMEOUT_MSECS = 10000 111}; 112 113struct mlx4_cmd_context { 114 struct completion done; 115 int result; 116 int next; 117 u64 out_param; 118 u16 token; 119 u8 fw_status; 120}; 121 122static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave, 123 struct mlx4_vhcr_cmd *in_vhcr); 124 125static int mlx4_status_to_errno(u8 status) 126{ 127 static const int trans_table[] = { 128 [CMD_STAT_INTERNAL_ERR] = -EIO, 129 [CMD_STAT_BAD_OP] = -EPERM, 130 [CMD_STAT_BAD_PARAM] = -EINVAL, 131 [CMD_STAT_BAD_SYS_STATE] = -ENXIO, 132 [CMD_STAT_BAD_RESOURCE] = -EBADF, 133 [CMD_STAT_RESOURCE_BUSY] = -EBUSY, 134 [CMD_STAT_EXCEED_LIM] = -ENOMEM, 135 [CMD_STAT_BAD_RES_STATE] = -EBADF, 136 [CMD_STAT_BAD_INDEX] = -EBADF, 137 [CMD_STAT_BAD_NVMEM] = -EFAULT, 138 [CMD_STAT_ICM_ERROR] = -ENFILE, 139 [CMD_STAT_BAD_QP_STATE] = -EINVAL, 140 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT, 141 [CMD_STAT_REG_BOUND] = -EBUSY, 142 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN, 143 [CMD_STAT_BAD_PKT] = -EINVAL, 144 [CMD_STAT_BAD_SIZE] = -ENOMEM, 145 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES, 146 }; 147 148 if (status >= ARRAY_SIZE(trans_table) || 149 (status != CMD_STAT_OK && trans_table[status] == 0)) 150 return -EIO; 151 152 return trans_table[status]; 153} 154 155static u8 mlx4_errno_to_status(int errno) 156{ 157 switch (errno) { 158 case -EPERM: 159 return CMD_STAT_BAD_OP; 160 case -EINVAL: 161 return CMD_STAT_BAD_PARAM; 162 case -ENXIO: 163 return CMD_STAT_BAD_SYS_STATE; 164 case -EBUSY: 165 return CMD_STAT_RESOURCE_BUSY; 166 case -ENOMEM: 167 return CMD_STAT_EXCEED_LIM; 168 case -ENFILE: 169 return CMD_STAT_ICM_ERROR; 170 default: 171 return CMD_STAT_INTERNAL_ERR; 172 } 173} 174 175static int comm_pending(struct mlx4_dev *dev) 176{ 177 struct mlx4_priv *priv = mlx4_priv(dev); 178 u32 status = readl(&priv->mfunc.comm->slave_read); 179 180 return (swab32(status) >> 31) != priv->cmd.comm_toggle; 181} 182 183static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param) 184{ 185 struct mlx4_priv *priv = mlx4_priv(dev); 186 u32 val; 187 188 priv->cmd.comm_toggle ^= 1; 189 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31); 190 __raw_writel((__force u32) cpu_to_be32(val), 191 &priv->mfunc.comm->slave_write); 192 mmiowb(); 193} 194 195static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param, 196 unsigned long timeout) 197{ 198 struct mlx4_priv *priv = mlx4_priv(dev); 199 unsigned long end; 200 int err = 0; 201 int ret_from_pending = 0; 202 203 /* First, verify that the master reports correct status */ 204 if (comm_pending(dev)) { 205 mlx4_warn(dev, "Communication channel is not idle." 206 "my toggle is %d (cmd:0x%x)\n", 207 priv->cmd.comm_toggle, cmd); 208 return -EAGAIN; 209 } 210 211 /* Write command */ 212 down(&priv->cmd.poll_sem); 213 mlx4_comm_cmd_post(dev, cmd, param); 214 215 end = msecs_to_jiffies(timeout) + jiffies; 216 while (comm_pending(dev) && time_before(jiffies, end)) 217 cond_resched(); 218 ret_from_pending = comm_pending(dev); 219 if (ret_from_pending) { 220 /* check if the slave is trying to boot in the middle of 221 * FLR process. The only non-zero result in the RESET command 222 * is MLX4_DELAY_RESET_SLAVE*/ 223 if ((MLX4_COMM_CMD_RESET == cmd)) { 224 mlx4_warn(dev, "Got slave FLRed from Communication" 225 " channel (ret:0x%x)\n", ret_from_pending); 226 err = MLX4_DELAY_RESET_SLAVE; 227 } else { 228 mlx4_warn(dev, "Communication channel timed out\n"); 229 err = -ETIMEDOUT; 230 } 231 } 232 233 up(&priv->cmd.poll_sem); 234 return err; 235} 236 237static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op, 238 u16 param, unsigned long timeout) 239{ 240 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 241 struct mlx4_cmd_context *context; 242 unsigned long end; 243 int err = 0; 244 245 down(&cmd->event_sem); 246 247 spin_lock(&cmd->context_lock); 248 BUG_ON(cmd->free_head < 0); 249 context = &cmd->context[cmd->free_head]; 250 context->token += cmd->token_mask + 1; 251 cmd->free_head = context->next; 252 spin_unlock(&cmd->context_lock); 253 254 init_completion(&context->done); 255 256 mlx4_comm_cmd_post(dev, op, param); 257 258 if (!wait_for_completion_timeout(&context->done, 259 msecs_to_jiffies(timeout))) { 260 err = -EBUSY; 261 goto out; 262 } 263 264 err = context->result; 265 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) { 266 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", 267 op, context->fw_status); 268 goto out; 269 } 270 271out: 272 /* wait for comm channel ready 273 * this is necessary for prevention the race 274 * when switching between event to polling mode 275 */ 276 end = msecs_to_jiffies(timeout) + jiffies; 277 while (comm_pending(dev) && time_before(jiffies, end)) 278 cond_resched(); 279 280 spin_lock(&cmd->context_lock); 281 context->next = cmd->free_head; 282 cmd->free_head = context - cmd->context; 283 spin_unlock(&cmd->context_lock); 284 285 up(&cmd->event_sem); 286 return err; 287} 288 289int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 290 unsigned long timeout) 291{ 292 if (mlx4_priv(dev)->cmd.use_events) 293 return mlx4_comm_cmd_wait(dev, cmd, param, timeout); 294 return mlx4_comm_cmd_poll(dev, cmd, param, timeout); 295} 296 297static int cmd_pending(struct mlx4_dev *dev) 298{ 299 u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); 300 301 return (status & swab32(1 << HCR_GO_BIT)) || 302 (mlx4_priv(dev)->cmd.toggle == 303 !!(status & swab32(1 << HCR_T_BIT))); 304} 305 306static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param, 307 u32 in_modifier, u8 op_modifier, u16 op, u16 token, 308 int event) 309{ 310 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 311 u32 __iomem *hcr = cmd->hcr; 312 int ret = -EAGAIN; 313 unsigned long end; 314 315 mutex_lock(&cmd->hcr_mutex); 316 317 end = jiffies; 318 if (event) 319 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS); 320 321 while (cmd_pending(dev)) { 322 if (time_after_eq(jiffies, end)) { 323 mlx4_err(dev, "%s:cmd_pending failed\n", __func__); 324 goto out; 325 } 326 cond_resched(); 327 } 328 329 /* 330 * We use writel (instead of something like memcpy_toio) 331 * because writes of less than 32 bits to the HCR don't work 332 * (and some architectures such as ia64 implement memcpy_toio 333 * in terms of writeb). 334 */ 335 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0); 336 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1); 337 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2); 338 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3); 339 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4); 340 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5); 341 342 /* __raw_writel may not order writes. */ 343 wmb(); 344 345 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 346 (cmd->toggle << HCR_T_BIT) | 347 (event ? (1 << HCR_E_BIT) : 0) | 348 (op_modifier << HCR_OPMOD_SHIFT) | 349 op), hcr + 6); 350 351 /* 352 * Make sure that our HCR writes don't get mixed in with 353 * writes from another CPU starting a FW command. 354 */ 355 mmiowb(); 356 357 cmd->toggle = cmd->toggle ^ 1; 358 359 ret = 0; 360 361out: 362 mutex_unlock(&cmd->hcr_mutex); 363 return ret; 364} 365 366static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 367 int out_is_imm, u32 in_modifier, u8 op_modifier, 368 u16 op, unsigned long timeout) 369{ 370 struct mlx4_priv *priv = mlx4_priv(dev); 371 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr; 372 int ret; 373 374 down(&priv->cmd.slave_sem); 375 vhcr->in_param = cpu_to_be64(in_param); 376 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0; 377 vhcr->in_modifier = cpu_to_be32(in_modifier); 378 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff)); 379 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN); 380 vhcr->status = 0; 381 vhcr->flags = !!(priv->cmd.use_events) << 6; 382 if (mlx4_is_master(dev)) { 383 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr); 384 if (!ret) { 385 if (out_is_imm) { 386 if (out_param) 387 *out_param = 388 be64_to_cpu(vhcr->out_param); 389 else { 390 mlx4_err(dev, "response expected while" 391 "output mailbox is NULL for " 392 "command 0x%x\n", op); 393 vhcr->status = CMD_STAT_BAD_PARAM; 394 } 395 } 396 ret = mlx4_status_to_errno(vhcr->status); 397 } 398 } else { 399 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, 400 MLX4_COMM_TIME + timeout); 401 if (!ret) { 402 if (out_is_imm) { 403 if (out_param) 404 *out_param = 405 be64_to_cpu(vhcr->out_param); 406 else { 407 mlx4_err(dev, "response expected while" 408 "output mailbox is NULL for " 409 "command 0x%x\n", op); 410 vhcr->status = CMD_STAT_BAD_PARAM; 411 } 412 } 413 ret = mlx4_status_to_errno(vhcr->status); 414 } else 415 mlx4_err(dev, "failed execution of VHCR_POST command" 416 "opcode 0x%x\n", op); 417 } 418 up(&priv->cmd.slave_sem); 419 return ret; 420} 421 422static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 423 int out_is_imm, u32 in_modifier, u8 op_modifier, 424 u16 op, unsigned long timeout) 425{ 426 struct mlx4_priv *priv = mlx4_priv(dev); 427 void __iomem *hcr = priv->cmd.hcr; 428 int err = 0; 429 unsigned long end; 430 u32 stat; 431 432 down(&priv->cmd.poll_sem); 433 434 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, 435 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0); 436 if (err) 437 goto out; 438 439 end = msecs_to_jiffies(timeout) + jiffies; 440 while (cmd_pending(dev) && time_before(jiffies, end)) 441 cond_resched(); 442 443 if (cmd_pending(dev)) { 444 err = -ETIMEDOUT; 445 goto out; 446 } 447 448 if (out_is_imm) 449 *out_param = 450 (u64) be32_to_cpu((__force __be32) 451 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | 452 (u64) be32_to_cpu((__force __be32) 453 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); 454 stat = be32_to_cpu((__force __be32) 455 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24; 456 err = mlx4_status_to_errno(stat); 457 if (err) 458 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", 459 op, stat); 460 461out: 462 up(&priv->cmd.poll_sem); 463 return err; 464} 465 466void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param) 467{ 468 struct mlx4_priv *priv = mlx4_priv(dev); 469 struct mlx4_cmd_context *context = 470 &priv->cmd.context[token & priv->cmd.token_mask]; 471 472 /* previously timed out command completing at long last */ 473 if (token != context->token) 474 return; 475 476 context->fw_status = status; 477 context->result = mlx4_status_to_errno(status); 478 context->out_param = out_param; 479 480 complete(&context->done); 481} 482 483static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 484 int out_is_imm, u32 in_modifier, u8 op_modifier, 485 u16 op, unsigned long timeout) 486{ 487 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 488 struct mlx4_cmd_context *context; 489 int err = 0; 490 491 down(&cmd->event_sem); 492 493 spin_lock(&cmd->context_lock); 494 BUG_ON(cmd->free_head < 0); 495 context = &cmd->context[cmd->free_head]; 496 context->token += cmd->token_mask + 1; 497 cmd->free_head = context->next; 498 spin_unlock(&cmd->context_lock); 499 500 init_completion(&context->done); 501 502 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, 503 in_modifier, op_modifier, op, context->token, 1); 504 505 if (!wait_for_completion_timeout(&context->done, 506 msecs_to_jiffies(timeout))) { 507 err = -EBUSY; 508 goto out; 509 } 510 511 err = context->result; 512 if (err) { 513 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", 514 op, context->fw_status); 515 goto out; 516 } 517 518 if (out_is_imm) 519 *out_param = context->out_param; 520 521out: 522 spin_lock(&cmd->context_lock); 523 context->next = cmd->free_head; 524 cmd->free_head = context - cmd->context; 525 spin_unlock(&cmd->context_lock); 526 527 up(&cmd->event_sem); 528 return err; 529} 530 531int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 532 int out_is_imm, u32 in_modifier, u8 op_modifier, 533 u16 op, unsigned long timeout, int native) 534{ 535 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) { 536 if (mlx4_priv(dev)->cmd.use_events) 537 return mlx4_cmd_wait(dev, in_param, out_param, 538 out_is_imm, in_modifier, 539 op_modifier, op, timeout); 540 else 541 return mlx4_cmd_poll(dev, in_param, out_param, 542 out_is_imm, in_modifier, 543 op_modifier, op, timeout); 544 } 545 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm, 546 in_modifier, op_modifier, op, timeout); 547} 548EXPORT_SYMBOL_GPL(__mlx4_cmd); 549 550 551static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev) 552{ 553 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL, 554 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 555} 556 557static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr, 558 int slave, u64 slave_addr, 559 int size, int is_read) 560{ 561 u64 in_param; 562 u64 out_param; 563 564 if ((slave_addr & 0xfff) | (master_addr & 0xfff) | 565 (slave & ~0x7f) | (size & 0xff)) { 566 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx " 567 "master_addr:0x%llx slave_id:%d size:%d\n", 568 slave_addr, master_addr, slave, size); 569 return -EINVAL; 570 } 571 572 if (is_read) { 573 in_param = (u64) slave | slave_addr; 574 out_param = (u64) dev->caps.function | master_addr; 575 } else { 576 in_param = (u64) dev->caps.function | master_addr; 577 out_param = (u64) slave | slave_addr; 578 } 579 580 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0, 581 MLX4_CMD_ACCESS_MEM, 582 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 583} 584 585int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 586 struct mlx4_vhcr *vhcr, 587 struct mlx4_cmd_mailbox *inbox, 588 struct mlx4_cmd_mailbox *outbox, 589 struct mlx4_cmd_info *cmd) 590{ 591 u64 in_param; 592 u64 out_param; 593 int err; 594 595 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param; 596 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param; 597 if (cmd->encode_slave_id) { 598 in_param &= 0xffffffffffffff00ll; 599 in_param |= slave; 600 } 601 602 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm, 603 vhcr->in_modifier, vhcr->op_modifier, vhcr->op, 604 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 605 606 if (cmd->out_is_imm) 607 vhcr->out_param = out_param; 608 609 return err; 610} 611 612static struct mlx4_cmd_info cmd_info[] = { 613 { 614 .opcode = MLX4_CMD_QUERY_FW, 615 .has_inbox = false, 616 .has_outbox = true, 617 .out_is_imm = false, 618 .encode_slave_id = false, 619 .verify = NULL, 620 .wrapper = NULL 621 }, 622 { 623 .opcode = MLX4_CMD_QUERY_HCA, 624 .has_inbox = false, 625 .has_outbox = true, 626 .out_is_imm = false, 627 .encode_slave_id = false, 628 .verify = NULL, 629 .wrapper = NULL 630 }, 631 { 632 .opcode = MLX4_CMD_QUERY_DEV_CAP, 633 .has_inbox = false, 634 .has_outbox = true, 635 .out_is_imm = false, 636 .encode_slave_id = false, 637 .verify = NULL, 638 .wrapper = NULL 639 }, 640 { 641 .opcode = MLX4_CMD_QUERY_FUNC_CAP, 642 .has_inbox = false, 643 .has_outbox = true, 644 .out_is_imm = false, 645 .encode_slave_id = false, 646 .verify = NULL, 647 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper 648 }, 649 { 650 .opcode = MLX4_CMD_QUERY_ADAPTER, 651 .has_inbox = false, 652 .has_outbox = true, 653 .out_is_imm = false, 654 .encode_slave_id = false, 655 .verify = NULL, 656 .wrapper = NULL 657 }, 658 { 659 .opcode = MLX4_CMD_INIT_PORT, 660 .has_inbox = false, 661 .has_outbox = false, 662 .out_is_imm = false, 663 .encode_slave_id = false, 664 .verify = NULL, 665 .wrapper = mlx4_INIT_PORT_wrapper 666 }, 667 { 668 .opcode = MLX4_CMD_CLOSE_PORT, 669 .has_inbox = false, 670 .has_outbox = false, 671 .out_is_imm = false, 672 .encode_slave_id = false, 673 .verify = NULL, 674 .wrapper = mlx4_CLOSE_PORT_wrapper 675 }, 676 { 677 .opcode = MLX4_CMD_QUERY_PORT, 678 .has_inbox = false, 679 .has_outbox = true, 680 .out_is_imm = false, 681 .encode_slave_id = false, 682 .verify = NULL, 683 .wrapper = mlx4_QUERY_PORT_wrapper 684 }, 685 { 686 .opcode = MLX4_CMD_SET_PORT, 687 .has_inbox = true, 688 .has_outbox = false, 689 .out_is_imm = false, 690 .encode_slave_id = false, 691 .verify = NULL, 692 .wrapper = mlx4_SET_PORT_wrapper 693 }, 694 { 695 .opcode = MLX4_CMD_MAP_EQ, 696 .has_inbox = false, 697 .has_outbox = false, 698 .out_is_imm = false, 699 .encode_slave_id = false, 700 .verify = NULL, 701 .wrapper = mlx4_MAP_EQ_wrapper 702 }, 703 { 704 .opcode = MLX4_CMD_SW2HW_EQ, 705 .has_inbox = true, 706 .has_outbox = false, 707 .out_is_imm = false, 708 .encode_slave_id = true, 709 .verify = NULL, 710 .wrapper = mlx4_SW2HW_EQ_wrapper 711 }, 712 { 713 .opcode = MLX4_CMD_HW_HEALTH_CHECK, 714 .has_inbox = false, 715 .has_outbox = false, 716 .out_is_imm = false, 717 .encode_slave_id = false, 718 .verify = NULL, 719 .wrapper = NULL 720 }, 721 { 722 .opcode = MLX4_CMD_NOP, 723 .has_inbox = false, 724 .has_outbox = false, 725 .out_is_imm = false, 726 .encode_slave_id = false, 727 .verify = NULL, 728 .wrapper = NULL 729 }, 730 { 731 .opcode = MLX4_CMD_ALLOC_RES, 732 .has_inbox = false, 733 .has_outbox = false, 734 .out_is_imm = true, 735 .encode_slave_id = false, 736 .verify = NULL, 737 .wrapper = mlx4_ALLOC_RES_wrapper 738 }, 739 { 740 .opcode = MLX4_CMD_FREE_RES, 741 .has_inbox = false, 742 .has_outbox = false, 743 .out_is_imm = false, 744 .encode_slave_id = false, 745 .verify = NULL, 746 .wrapper = mlx4_FREE_RES_wrapper 747 }, 748 { 749 .opcode = MLX4_CMD_SW2HW_MPT, 750 .has_inbox = true, 751 .has_outbox = false, 752 .out_is_imm = false, 753 .encode_slave_id = true, 754 .verify = NULL, 755 .wrapper = mlx4_SW2HW_MPT_wrapper 756 }, 757 { 758 .opcode = MLX4_CMD_QUERY_MPT, 759 .has_inbox = false, 760 .has_outbox = true, 761 .out_is_imm = false, 762 .encode_slave_id = false, 763 .verify = NULL, 764 .wrapper = mlx4_QUERY_MPT_wrapper 765 }, 766 { 767 .opcode = MLX4_CMD_HW2SW_MPT, 768 .has_inbox = false, 769 .has_outbox = false, 770 .out_is_imm = false, 771 .encode_slave_id = false, 772 .verify = NULL, 773 .wrapper = mlx4_HW2SW_MPT_wrapper 774 }, 775 { 776 .opcode = MLX4_CMD_READ_MTT, 777 .has_inbox = false, 778 .has_outbox = true, 779 .out_is_imm = false, 780 .encode_slave_id = false, 781 .verify = NULL, 782 .wrapper = NULL 783 }, 784 { 785 .opcode = MLX4_CMD_WRITE_MTT, 786 .has_inbox = true, 787 .has_outbox = false, 788 .out_is_imm = false, 789 .encode_slave_id = false, 790 .verify = NULL, 791 .wrapper = mlx4_WRITE_MTT_wrapper 792 }, 793 { 794 .opcode = MLX4_CMD_SYNC_TPT, 795 .has_inbox = true, 796 .has_outbox = false, 797 .out_is_imm = false, 798 .encode_slave_id = false, 799 .verify = NULL, 800 .wrapper = NULL 801 }, 802 { 803 .opcode = MLX4_CMD_HW2SW_EQ, 804 .has_inbox = false, 805 .has_outbox = true, 806 .out_is_imm = false, 807 .encode_slave_id = true, 808 .verify = NULL, 809 .wrapper = mlx4_HW2SW_EQ_wrapper 810 }, 811 { 812 .opcode = MLX4_CMD_QUERY_EQ, 813 .has_inbox = false, 814 .has_outbox = true, 815 .out_is_imm = false, 816 .encode_slave_id = true, 817 .verify = NULL, 818 .wrapper = mlx4_QUERY_EQ_wrapper 819 }, 820 { 821 .opcode = MLX4_CMD_SW2HW_CQ, 822 .has_inbox = true, 823 .has_outbox = false, 824 .out_is_imm = false, 825 .encode_slave_id = true, 826 .verify = NULL, 827 .wrapper = mlx4_SW2HW_CQ_wrapper 828 }, 829 { 830 .opcode = MLX4_CMD_HW2SW_CQ, 831 .has_inbox = false, 832 .has_outbox = false, 833 .out_is_imm = false, 834 .encode_slave_id = false, 835 .verify = NULL, 836 .wrapper = mlx4_HW2SW_CQ_wrapper 837 }, 838 { 839 .opcode = MLX4_CMD_QUERY_CQ, 840 .has_inbox = false, 841 .has_outbox = true, 842 .out_is_imm = false, 843 .encode_slave_id = false, 844 .verify = NULL, 845 .wrapper = mlx4_QUERY_CQ_wrapper 846 }, 847 { 848 .opcode = MLX4_CMD_MODIFY_CQ, 849 .has_inbox = true, 850 .has_outbox = false, 851 .out_is_imm = true, 852 .encode_slave_id = false, 853 .verify = NULL, 854 .wrapper = mlx4_MODIFY_CQ_wrapper 855 }, 856 { 857 .opcode = MLX4_CMD_SW2HW_SRQ, 858 .has_inbox = true, 859 .has_outbox = false, 860 .out_is_imm = false, 861 .encode_slave_id = true, 862 .verify = NULL, 863 .wrapper = mlx4_SW2HW_SRQ_wrapper 864 }, 865 { 866 .opcode = MLX4_CMD_HW2SW_SRQ, 867 .has_inbox = false, 868 .has_outbox = false, 869 .out_is_imm = false, 870 .encode_slave_id = false, 871 .verify = NULL, 872 .wrapper = mlx4_HW2SW_SRQ_wrapper 873 }, 874 { 875 .opcode = MLX4_CMD_QUERY_SRQ, 876 .has_inbox = false, 877 .has_outbox = true, 878 .out_is_imm = false, 879 .encode_slave_id = false, 880 .verify = NULL, 881 .wrapper = mlx4_QUERY_SRQ_wrapper 882 }, 883 { 884 .opcode = MLX4_CMD_ARM_SRQ, 885 .has_inbox = false, 886 .has_outbox = false, 887 .out_is_imm = false, 888 .encode_slave_id = false, 889 .verify = NULL, 890 .wrapper = mlx4_ARM_SRQ_wrapper 891 }, 892 { 893 .opcode = MLX4_CMD_RST2INIT_QP, 894 .has_inbox = true, 895 .has_outbox = false, 896 .out_is_imm = false, 897 .encode_slave_id = true, 898 .verify = NULL, 899 .wrapper = mlx4_RST2INIT_QP_wrapper 900 }, 901 { 902 .opcode = MLX4_CMD_INIT2INIT_QP, 903 .has_inbox = true, 904 .has_outbox = false, 905 .out_is_imm = false, 906 .encode_slave_id = false, 907 .verify = NULL, 908 .wrapper = mlx4_GEN_QP_wrapper 909 }, 910 { 911 .opcode = MLX4_CMD_INIT2RTR_QP, 912 .has_inbox = true, 913 .has_outbox = false, 914 .out_is_imm = false, 915 .encode_slave_id = false, 916 .verify = NULL, 917 .wrapper = mlx4_INIT2RTR_QP_wrapper 918 }, 919 { 920 .opcode = MLX4_CMD_RTR2RTS_QP, 921 .has_inbox = true, 922 .has_outbox = false, 923 .out_is_imm = false, 924 .encode_slave_id = false, 925 .verify = NULL, 926 .wrapper = mlx4_GEN_QP_wrapper 927 }, 928 { 929 .opcode = MLX4_CMD_RTS2RTS_QP, 930 .has_inbox = true, 931 .has_outbox = false, 932 .out_is_imm = false, 933 .encode_slave_id = false, 934 .verify = NULL, 935 .wrapper = mlx4_GEN_QP_wrapper 936 }, 937 { 938 .opcode = MLX4_CMD_SQERR2RTS_QP, 939 .has_inbox = true, 940 .has_outbox = false, 941 .out_is_imm = false, 942 .encode_slave_id = false, 943 .verify = NULL, 944 .wrapper = mlx4_GEN_QP_wrapper 945 }, 946 { 947 .opcode = MLX4_CMD_2ERR_QP, 948 .has_inbox = false, 949 .has_outbox = false, 950 .out_is_imm = false, 951 .encode_slave_id = false, 952 .verify = NULL, 953 .wrapper = mlx4_GEN_QP_wrapper 954 }, 955 { 956 .opcode = MLX4_CMD_RTS2SQD_QP, 957 .has_inbox = false, 958 .has_outbox = false, 959 .out_is_imm = false, 960 .encode_slave_id = false, 961 .verify = NULL, 962 .wrapper = mlx4_GEN_QP_wrapper 963 }, 964 { 965 .opcode = MLX4_CMD_SQD2SQD_QP, 966 .has_inbox = true, 967 .has_outbox = false, 968 .out_is_imm = false, 969 .encode_slave_id = false, 970 .verify = NULL, 971 .wrapper = mlx4_GEN_QP_wrapper 972 }, 973 { 974 .opcode = MLX4_CMD_SQD2RTS_QP, 975 .has_inbox = true, 976 .has_outbox = false, 977 .out_is_imm = false, 978 .encode_slave_id = false, 979 .verify = NULL, 980 .wrapper = mlx4_GEN_QP_wrapper 981 }, 982 { 983 .opcode = MLX4_CMD_2RST_QP, 984 .has_inbox = false, 985 .has_outbox = false, 986 .out_is_imm = false, 987 .encode_slave_id = false, 988 .verify = NULL, 989 .wrapper = mlx4_2RST_QP_wrapper 990 }, 991 { 992 .opcode = MLX4_CMD_QUERY_QP, 993 .has_inbox = false, 994 .has_outbox = true, 995 .out_is_imm = false, 996 .encode_slave_id = false, 997 .verify = NULL, 998 .wrapper = mlx4_GEN_QP_wrapper 999 }, 1000 { 1001 .opcode = MLX4_CMD_SUSPEND_QP, 1002 .has_inbox = false, 1003 .has_outbox = false, 1004 .out_is_imm = false, 1005 .encode_slave_id = false, 1006 .verify = NULL, 1007 .wrapper = mlx4_GEN_QP_wrapper 1008 }, 1009 { 1010 .opcode = MLX4_CMD_UNSUSPEND_QP, 1011 .has_inbox = false, 1012 .has_outbox = false, 1013 .out_is_imm = false, 1014 .encode_slave_id = false, 1015 .verify = NULL, 1016 .wrapper = mlx4_GEN_QP_wrapper 1017 }, 1018 { 1019 .opcode = MLX4_CMD_QUERY_IF_STAT, 1020 .has_inbox = false, 1021 .has_outbox = true, 1022 .out_is_imm = false, 1023 .encode_slave_id = false, 1024 .verify = NULL, 1025 .wrapper = mlx4_QUERY_IF_STAT_wrapper 1026 }, 1027 /* Native multicast commands are not available for guests */ 1028 { 1029 .opcode = MLX4_CMD_QP_ATTACH, 1030 .has_inbox = true, 1031 .has_outbox = false, 1032 .out_is_imm = false, 1033 .encode_slave_id = false, 1034 .verify = NULL, 1035 .wrapper = mlx4_QP_ATTACH_wrapper 1036 }, 1037 { 1038 .opcode = MLX4_CMD_PROMISC, 1039 .has_inbox = false, 1040 .has_outbox = false, 1041 .out_is_imm = false, 1042 .encode_slave_id = false, 1043 .verify = NULL, 1044 .wrapper = mlx4_PROMISC_wrapper 1045 }, 1046 /* Ethernet specific commands */ 1047 { 1048 .opcode = MLX4_CMD_SET_VLAN_FLTR, 1049 .has_inbox = true, 1050 .has_outbox = false, 1051 .out_is_imm = false, 1052 .encode_slave_id = false, 1053 .verify = NULL, 1054 .wrapper = mlx4_SET_VLAN_FLTR_wrapper 1055 }, 1056 { 1057 .opcode = MLX4_CMD_SET_MCAST_FLTR, 1058 .has_inbox = false, 1059 .has_outbox = false, 1060 .out_is_imm = false, 1061 .encode_slave_id = false, 1062 .verify = NULL, 1063 .wrapper = mlx4_SET_MCAST_FLTR_wrapper 1064 }, 1065 { 1066 .opcode = MLX4_CMD_DUMP_ETH_STATS, 1067 .has_inbox = false, 1068 .has_outbox = true, 1069 .out_is_imm = false, 1070 .encode_slave_id = false, 1071 .verify = NULL, 1072 .wrapper = mlx4_DUMP_ETH_STATS_wrapper 1073 }, 1074 { 1075 .opcode = MLX4_CMD_INFORM_FLR_DONE, 1076 .has_inbox = false, 1077 .has_outbox = false, 1078 .out_is_imm = false, 1079 .encode_slave_id = false, 1080 .verify = NULL, 1081 .wrapper = NULL 1082 }, 1083}; 1084 1085static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave, 1086 struct mlx4_vhcr_cmd *in_vhcr) 1087{ 1088 struct mlx4_priv *priv = mlx4_priv(dev); 1089 struct mlx4_cmd_info *cmd = NULL; 1090 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr; 1091 struct mlx4_vhcr *vhcr; 1092 struct mlx4_cmd_mailbox *inbox = NULL; 1093 struct mlx4_cmd_mailbox *outbox = NULL; 1094 u64 in_param; 1095 u64 out_param; 1096 int ret = 0; 1097 int i; 1098 int err = 0; 1099 1100 /* Create sw representation of Virtual HCR */ 1101 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL); 1102 if (!vhcr) 1103 return -ENOMEM; 1104 1105 /* DMA in the vHCR */ 1106 if (!in_vhcr) { 1107 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, 1108 priv->mfunc.master.slave_state[slave].vhcr_dma, 1109 ALIGN(sizeof(struct mlx4_vhcr_cmd), 1110 MLX4_ACCESS_MEM_ALIGN), 1); 1111 if (ret) { 1112 mlx4_err(dev, "%s:Failed reading vhcr" 1113 "ret: 0x%x\n", __func__, ret); 1114 kfree(vhcr); 1115 return ret; 1116 } 1117 } 1118 1119 /* Fill SW VHCR fields */ 1120 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param); 1121 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param); 1122 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier); 1123 vhcr->token = be16_to_cpu(vhcr_cmd->token); 1124 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff; 1125 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12); 1126 vhcr->e_bit = vhcr_cmd->flags & (1 << 6); 1127 1128 /* Lookup command */ 1129 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) { 1130 if (vhcr->op == cmd_info[i].opcode) { 1131 cmd = &cmd_info[i]; 1132 break; 1133 } 1134 } 1135 if (!cmd) { 1136 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n", 1137 vhcr->op, slave); 1138 vhcr_cmd->status = CMD_STAT_BAD_PARAM; 1139 goto out_status; 1140 } 1141 1142 /* Read inbox */ 1143 if (cmd->has_inbox) { 1144 vhcr->in_param &= INBOX_MASK; 1145 inbox = mlx4_alloc_cmd_mailbox(dev); 1146 if (IS_ERR(inbox)) { 1147 vhcr_cmd->status = CMD_STAT_BAD_SIZE; 1148 inbox = NULL; 1149 goto out_status; 1150 } 1151 1152 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave, 1153 vhcr->in_param, 1154 MLX4_MAILBOX_SIZE, 1)) { 1155 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n", 1156 __func__, cmd->opcode); 1157 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR; 1158 goto out_status; 1159 } 1160 } 1161 1162 /* Apply permission and bound checks if applicable */ 1163 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) { 1164 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection " 1165 "checks for resource_id:%d\n", vhcr->op, slave, 1166 vhcr->in_modifier); 1167 vhcr_cmd->status = CMD_STAT_BAD_OP; 1168 goto out_status; 1169 } 1170 1171 /* Allocate outbox */ 1172 if (cmd->has_outbox) { 1173 outbox = mlx4_alloc_cmd_mailbox(dev); 1174 if (IS_ERR(outbox)) { 1175 vhcr_cmd->status = CMD_STAT_BAD_SIZE; 1176 outbox = NULL; 1177 goto out_status; 1178 } 1179 } 1180 1181 /* Execute the command! */ 1182 if (cmd->wrapper) { 1183 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox, 1184 cmd); 1185 if (cmd->out_is_imm) 1186 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); 1187 } else { 1188 in_param = cmd->has_inbox ? (u64) inbox->dma : 1189 vhcr->in_param; 1190 out_param = cmd->has_outbox ? (u64) outbox->dma : 1191 vhcr->out_param; 1192 err = __mlx4_cmd(dev, in_param, &out_param, 1193 cmd->out_is_imm, vhcr->in_modifier, 1194 vhcr->op_modifier, vhcr->op, 1195 MLX4_CMD_TIME_CLASS_A, 1196 MLX4_CMD_NATIVE); 1197 1198 if (cmd->out_is_imm) { 1199 vhcr->out_param = out_param; 1200 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); 1201 } 1202 } 1203 1204 if (err) { 1205 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with" 1206 " error:%d, status %d\n", 1207 vhcr->op, slave, vhcr->errno, err); 1208 vhcr_cmd->status = mlx4_errno_to_status(err); 1209 goto out_status; 1210 } 1211 1212 1213 /* Write outbox if command completed successfully */ 1214 if (cmd->has_outbox && !vhcr_cmd->status) { 1215 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave, 1216 vhcr->out_param, 1217 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED); 1218 if (ret) { 1219 /* If we failed to write back the outbox after the 1220 *command was successfully executed, we must fail this 1221 * slave, as it is now in undefined state */ 1222 mlx4_err(dev, "%s:Failed writing outbox\n", __func__); 1223 goto out; 1224 } 1225 } 1226 1227out_status: 1228 /* DMA back vhcr result */ 1229 if (!in_vhcr) { 1230 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, 1231 priv->mfunc.master.slave_state[slave].vhcr_dma, 1232 ALIGN(sizeof(struct mlx4_vhcr), 1233 MLX4_ACCESS_MEM_ALIGN), 1234 MLX4_CMD_WRAPPED); 1235 if (ret) 1236 mlx4_err(dev, "%s:Failed writing vhcr result\n", 1237 __func__); 1238 else if (vhcr->e_bit && 1239 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe)) 1240 mlx4_warn(dev, "Failed to generate command completion " 1241 "eqe for slave %d\n", slave); 1242 } 1243 1244out: 1245 kfree(vhcr); 1246 mlx4_free_cmd_mailbox(dev, inbox); 1247 mlx4_free_cmd_mailbox(dev, outbox); 1248 return ret; 1249} 1250 1251static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd, 1252 u16 param, u8 toggle) 1253{ 1254 struct mlx4_priv *priv = mlx4_priv(dev); 1255 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 1256 u32 reply; 1257 u32 slave_status = 0; 1258 u8 is_going_down = 0; 1259 int i; 1260 1261 slave_state[slave].comm_toggle ^= 1; 1262 reply = (u32) slave_state[slave].comm_toggle << 31; 1263 if (toggle != slave_state[slave].comm_toggle) { 1264 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER" 1265 "STATE COMPROMISIED ***\n", toggle, slave); 1266 goto reset_slave; 1267 } 1268 if (cmd == MLX4_COMM_CMD_RESET) { 1269 mlx4_warn(dev, "Received reset from slave:%d\n", slave); 1270 slave_state[slave].active = false; 1271 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) { 1272 slave_state[slave].event_eq[i].eqn = -1; 1273 slave_state[slave].event_eq[i].token = 0; 1274 } 1275 /*check if we are in the middle of FLR process, 1276 if so return "retry" status to the slave*/ 1277 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) { 1278 slave_status = MLX4_DELAY_RESET_SLAVE; 1279 goto inform_slave_state; 1280 } 1281 1282 /* write the version in the event field */ 1283 reply |= mlx4_comm_get_version(); 1284 1285 goto reset_slave; 1286 } 1287 /*command from slave in the middle of FLR*/ 1288 if (cmd != MLX4_COMM_CMD_RESET && 1289 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) { 1290 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) " 1291 "in the middle of FLR\n", slave, cmd); 1292 return; 1293 } 1294 1295 switch (cmd) { 1296 case MLX4_COMM_CMD_VHCR0: 1297 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET) 1298 goto reset_slave; 1299 slave_state[slave].vhcr_dma = ((u64) param) << 48; 1300 priv->mfunc.master.slave_state[slave].cookie = 0; 1301 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]); 1302 break; 1303 case MLX4_COMM_CMD_VHCR1: 1304 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0) 1305 goto reset_slave; 1306 slave_state[slave].vhcr_dma |= ((u64) param) << 32; 1307 break; 1308 case MLX4_COMM_CMD_VHCR2: 1309 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1) 1310 goto reset_slave; 1311 slave_state[slave].vhcr_dma |= ((u64) param) << 16; 1312 break; 1313 case MLX4_COMM_CMD_VHCR_EN: 1314 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2) 1315 goto reset_slave; 1316 slave_state[slave].vhcr_dma |= param; 1317 slave_state[slave].active = true; 1318 break; 1319 case MLX4_COMM_CMD_VHCR_POST: 1320 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) && 1321 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) 1322 goto reset_slave; 1323 down(&priv->cmd.slave_sem); 1324 if (mlx4_master_process_vhcr(dev, slave, NULL)) { 1325 mlx4_err(dev, "Failed processing vhcr for slave:%d," 1326 " resetting slave.\n", slave); 1327 up(&priv->cmd.slave_sem); 1328 goto reset_slave; 1329 } 1330 up(&priv->cmd.slave_sem); 1331 break; 1332 default: 1333 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave); 1334 goto reset_slave; 1335 } 1336 spin_lock(&priv->mfunc.master.slave_state_lock); 1337 if (!slave_state[slave].is_slave_going_down) 1338 slave_state[slave].last_cmd = cmd; 1339 else 1340 is_going_down = 1; 1341 spin_unlock(&priv->mfunc.master.slave_state_lock); 1342 if (is_going_down) { 1343 mlx4_warn(dev, "Slave is going down aborting command(%d)" 1344 " executing from slave:%d\n", 1345 cmd, slave); 1346 return; 1347 } 1348 __raw_writel((__force u32) cpu_to_be32(reply), 1349 &priv->mfunc.comm[slave].slave_read); 1350 mmiowb(); 1351 1352 return; 1353 1354reset_slave: 1355 /* cleanup any slave resources */ 1356 mlx4_delete_all_resources_for_slave(dev, slave); 1357 spin_lock(&priv->mfunc.master.slave_state_lock); 1358 if (!slave_state[slave].is_slave_going_down) 1359 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET; 1360 spin_unlock(&priv->mfunc.master.slave_state_lock); 1361 /*with slave in the middle of flr, no need to clean resources again.*/ 1362inform_slave_state: 1363 memset(&slave_state[slave].event_eq, 0, 1364 sizeof(struct mlx4_slave_event_eq_info)); 1365 __raw_writel((__force u32) cpu_to_be32(reply), 1366 &priv->mfunc.comm[slave].slave_read); 1367 wmb(); 1368} 1369 1370/* master command processing */ 1371void mlx4_master_comm_channel(struct work_struct *work) 1372{ 1373 struct mlx4_mfunc_master_ctx *master = 1374 container_of(work, 1375 struct mlx4_mfunc_master_ctx, 1376 comm_work); 1377 struct mlx4_mfunc *mfunc = 1378 container_of(master, struct mlx4_mfunc, master); 1379 struct mlx4_priv *priv = 1380 container_of(mfunc, struct mlx4_priv, mfunc); 1381 struct mlx4_dev *dev = &priv->dev; 1382 __be32 *bit_vec; 1383 u32 comm_cmd; 1384 u32 vec; 1385 int i, j, slave; 1386 int toggle; 1387 int served = 0; 1388 int reported = 0; 1389 u32 slt; 1390 1391 bit_vec = master->comm_arm_bit_vector; 1392 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) { 1393 vec = be32_to_cpu(bit_vec[i]); 1394 for (j = 0; j < 32; j++) { 1395 if (!(vec & (1 << j))) 1396 continue; 1397 ++reported; 1398 slave = (i * 32) + j; 1399 comm_cmd = swab32(readl( 1400 &mfunc->comm[slave].slave_write)); 1401 slt = swab32(readl(&mfunc->comm[slave].slave_read)) 1402 >> 31; 1403 toggle = comm_cmd >> 31; 1404 if (toggle != slt) { 1405 if (master->slave_state[slave].comm_toggle 1406 != slt) { 1407 printk(KERN_INFO "slave %d out of sync." 1408 " read toggle %d, state toggle %d. " 1409 "Resynching.\n", slave, slt, 1410 master->slave_state[slave].comm_toggle); 1411 master->slave_state[slave].comm_toggle = 1412 slt; 1413 } 1414 mlx4_master_do_cmd(dev, slave, 1415 comm_cmd >> 16 & 0xff, 1416 comm_cmd & 0xffff, toggle); 1417 ++served; 1418 } 1419 } 1420 } 1421 1422 if (reported && reported != served) 1423 mlx4_warn(dev, "Got command event with bitmask from %d slaves" 1424 " but %d were served\n", 1425 reported, served); 1426 1427 if (mlx4_ARM_COMM_CHANNEL(dev)) 1428 mlx4_warn(dev, "Failed to arm comm channel events\n"); 1429} 1430 1431static int sync_toggles(struct mlx4_dev *dev) 1432{ 1433 struct mlx4_priv *priv = mlx4_priv(dev); 1434 int wr_toggle; 1435 int rd_toggle; 1436 unsigned long end; 1437 1438 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31; 1439 end = jiffies + msecs_to_jiffies(5000); 1440 1441 while (time_before(jiffies, end)) { 1442 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31; 1443 if (rd_toggle == wr_toggle) { 1444 priv->cmd.comm_toggle = rd_toggle; 1445 return 0; 1446 } 1447 1448 cond_resched(); 1449 } 1450 1451 /* 1452 * we could reach here if for example the previous VM using this 1453 * function misbehaved and left the channel with unsynced state. We 1454 * should fix this here and give this VM a chance to use a properly 1455 * synced channel 1456 */ 1457 mlx4_warn(dev, "recovering from previously mis-behaved VM\n"); 1458 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read); 1459 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write); 1460 priv->cmd.comm_toggle = 0; 1461 1462 return 0; 1463} 1464 1465int mlx4_multi_func_init(struct mlx4_dev *dev) 1466{ 1467 struct mlx4_priv *priv = mlx4_priv(dev); 1468 struct mlx4_slave_state *s_state; 1469 int i, j, err, port; 1470 1471 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE, 1472 &priv->mfunc.vhcr_dma, 1473 GFP_KERNEL); 1474 if (!priv->mfunc.vhcr) { 1475 mlx4_err(dev, "Couldn't allocate vhcr.\n"); 1476 return -ENOMEM; 1477 } 1478 1479 if (mlx4_is_master(dev)) 1480 priv->mfunc.comm = 1481 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) + 1482 priv->fw.comm_base, MLX4_COMM_PAGESIZE); 1483 else 1484 priv->mfunc.comm = 1485 ioremap(pci_resource_start(dev->pdev, 2) + 1486 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE); 1487 if (!priv->mfunc.comm) { 1488 mlx4_err(dev, "Couldn't map communication vector.\n"); 1489 goto err_vhcr; 1490 } 1491 1492 if (mlx4_is_master(dev)) { 1493 priv->mfunc.master.slave_state = 1494 kzalloc(dev->num_slaves * 1495 sizeof(struct mlx4_slave_state), GFP_KERNEL); 1496 if (!priv->mfunc.master.slave_state) 1497 goto err_comm; 1498 1499 for (i = 0; i < dev->num_slaves; ++i) { 1500 s_state = &priv->mfunc.master.slave_state[i]; 1501 s_state->last_cmd = MLX4_COMM_CMD_RESET; 1502 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j) 1503 s_state->event_eq[j].eqn = -1; 1504 __raw_writel((__force u32) 0, 1505 &priv->mfunc.comm[i].slave_write); 1506 __raw_writel((__force u32) 0, 1507 &priv->mfunc.comm[i].slave_read); 1508 mmiowb(); 1509 for (port = 1; port <= MLX4_MAX_PORTS; port++) { 1510 s_state->vlan_filter[port] = 1511 kzalloc(sizeof(struct mlx4_vlan_fltr), 1512 GFP_KERNEL); 1513 if (!s_state->vlan_filter[port]) { 1514 if (--port) 1515 kfree(s_state->vlan_filter[port]); 1516 goto err_slaves; 1517 } 1518 INIT_LIST_HEAD(&s_state->mcast_filters[port]); 1519 } 1520 spin_lock_init(&s_state->lock); 1521 } 1522 1523 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe)); 1524 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD; 1525 INIT_WORK(&priv->mfunc.master.comm_work, 1526 mlx4_master_comm_channel); 1527 INIT_WORK(&priv->mfunc.master.slave_event_work, 1528 mlx4_gen_slave_eqe); 1529 INIT_WORK(&priv->mfunc.master.slave_flr_event_work, 1530 mlx4_master_handle_slave_flr); 1531 spin_lock_init(&priv->mfunc.master.slave_state_lock); 1532 priv->mfunc.master.comm_wq = 1533 create_singlethread_workqueue("mlx4_comm"); 1534 if (!priv->mfunc.master.comm_wq) 1535 goto err_slaves; 1536 1537 if (mlx4_init_resource_tracker(dev)) 1538 goto err_thread; 1539 1540 sema_init(&priv->cmd.slave_sem, 1); 1541 err = mlx4_ARM_COMM_CHANNEL(dev); 1542 if (err) { 1543 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 1544 err); 1545 goto err_resource; 1546 } 1547 1548 } else { 1549 err = sync_toggles(dev); 1550 if (err) { 1551 mlx4_err(dev, "Couldn't sync toggles\n"); 1552 goto err_comm; 1553 } 1554 1555 sema_init(&priv->cmd.slave_sem, 1); 1556 } 1557 return 0; 1558 1559err_resource: 1560 mlx4_free_resource_tracker(dev); 1561err_thread: 1562 flush_workqueue(priv->mfunc.master.comm_wq); 1563 destroy_workqueue(priv->mfunc.master.comm_wq); 1564err_slaves: 1565 while (--i) { 1566 for (port = 1; port <= MLX4_MAX_PORTS; port++) 1567 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); 1568 } 1569 kfree(priv->mfunc.master.slave_state); 1570err_comm: 1571 iounmap(priv->mfunc.comm); 1572err_vhcr: 1573 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE, 1574 priv->mfunc.vhcr, 1575 priv->mfunc.vhcr_dma); 1576 priv->mfunc.vhcr = NULL; 1577 return -ENOMEM; 1578} 1579 1580int mlx4_cmd_init(struct mlx4_dev *dev) 1581{ 1582 struct mlx4_priv *priv = mlx4_priv(dev); 1583 1584 mutex_init(&priv->cmd.hcr_mutex); 1585 sema_init(&priv->cmd.poll_sem, 1); 1586 priv->cmd.use_events = 0; 1587 priv->cmd.toggle = 1; 1588 1589 priv->cmd.hcr = NULL; 1590 priv->mfunc.vhcr = NULL; 1591 1592 if (!mlx4_is_slave(dev)) { 1593 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + 1594 MLX4_HCR_BASE, MLX4_HCR_SIZE); 1595 if (!priv->cmd.hcr) { 1596 mlx4_err(dev, "Couldn't map command register.\n"); 1597 return -ENOMEM; 1598 } 1599 } 1600 1601 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev, 1602 MLX4_MAILBOX_SIZE, 1603 MLX4_MAILBOX_SIZE, 0); 1604 if (!priv->cmd.pool) 1605 goto err_hcr; 1606 1607 return 0; 1608 1609err_hcr: 1610 if (!mlx4_is_slave(dev)) 1611 iounmap(priv->cmd.hcr); 1612 return -ENOMEM; 1613} 1614 1615void mlx4_multi_func_cleanup(struct mlx4_dev *dev) 1616{ 1617 struct mlx4_priv *priv = mlx4_priv(dev); 1618 int i, port; 1619 1620 if (mlx4_is_master(dev)) { 1621 flush_workqueue(priv->mfunc.master.comm_wq); 1622 destroy_workqueue(priv->mfunc.master.comm_wq); 1623 for (i = 0; i < dev->num_slaves; i++) { 1624 for (port = 1; port <= MLX4_MAX_PORTS; port++) 1625 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); 1626 } 1627 kfree(priv->mfunc.master.slave_state); 1628 } 1629 1630 iounmap(priv->mfunc.comm); 1631 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE, 1632 priv->mfunc.vhcr, priv->mfunc.vhcr_dma); 1633 priv->mfunc.vhcr = NULL; 1634} 1635 1636void mlx4_cmd_cleanup(struct mlx4_dev *dev) 1637{ 1638 struct mlx4_priv *priv = mlx4_priv(dev); 1639 1640 pci_pool_destroy(priv->cmd.pool); 1641 1642 if (!mlx4_is_slave(dev)) 1643 iounmap(priv->cmd.hcr); 1644} 1645 1646/* 1647 * Switch to using events to issue FW commands (can only be called 1648 * after event queue for command events has been initialized). 1649 */ 1650int mlx4_cmd_use_events(struct mlx4_dev *dev) 1651{ 1652 struct mlx4_priv *priv = mlx4_priv(dev); 1653 int i; 1654 int err = 0; 1655 1656 priv->cmd.context = kmalloc(priv->cmd.max_cmds * 1657 sizeof (struct mlx4_cmd_context), 1658 GFP_KERNEL); 1659 if (!priv->cmd.context) 1660 return -ENOMEM; 1661 1662 for (i = 0; i < priv->cmd.max_cmds; ++i) { 1663 priv->cmd.context[i].token = i; 1664 priv->cmd.context[i].next = i + 1; 1665 } 1666 1667 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1; 1668 priv->cmd.free_head = 0; 1669 1670 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds); 1671 spin_lock_init(&priv->cmd.context_lock); 1672 1673 for (priv->cmd.token_mask = 1; 1674 priv->cmd.token_mask < priv->cmd.max_cmds; 1675 priv->cmd.token_mask <<= 1) 1676 ; /* nothing */ 1677 --priv->cmd.token_mask; 1678 1679 down(&priv->cmd.poll_sem); 1680 priv->cmd.use_events = 1; 1681 1682 return err; 1683} 1684 1685/* 1686 * Switch back to polling (used when shutting down the device) 1687 */ 1688void mlx4_cmd_use_polling(struct mlx4_dev *dev) 1689{ 1690 struct mlx4_priv *priv = mlx4_priv(dev); 1691 int i; 1692 1693 priv->cmd.use_events = 0; 1694 1695 for (i = 0; i < priv->cmd.max_cmds; ++i) 1696 down(&priv->cmd.event_sem); 1697 1698 kfree(priv->cmd.context); 1699 1700 up(&priv->cmd.poll_sem); 1701} 1702 1703struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev) 1704{ 1705 struct mlx4_cmd_mailbox *mailbox; 1706 1707 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL); 1708 if (!mailbox) 1709 return ERR_PTR(-ENOMEM); 1710 1711 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL, 1712 &mailbox->dma); 1713 if (!mailbox->buf) { 1714 kfree(mailbox); 1715 return ERR_PTR(-ENOMEM); 1716 } 1717 1718 return mailbox; 1719} 1720EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox); 1721 1722void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, 1723 struct mlx4_cmd_mailbox *mailbox) 1724{ 1725 if (!mailbox) 1726 return; 1727 1728 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma); 1729 kfree(mailbox); 1730} 1731EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox); 1732 1733u32 mlx4_comm_get_version(void) 1734{ 1735 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER; 1736} 1737