Lines Matching defs:efx
17 #include "efx.h"
171 static void txc_reset_logic(struct efx_nic *efx);
174 void falcon_txc_set_gpio_val(struct efx_nic *efx, int pin, int on)
176 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_OUTPUT, 1 << pin, on);
180 void falcon_txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir)
182 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_DIR, 1 << pin, dir);
187 static int txc_reset_phy(struct efx_nic *efx)
189 int rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PMAPMD,
196 rc = efx_mdio_check_mmds(efx, TXC_REQUIRED_DEVS);
203 netif_err(efx, hw, efx->net_dev, TXCNAME ": reset timed out!\n");
208 static int txc_bist_one(struct efx_nic *efx, int mmd, int test)
215 ctrl = efx_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL);
217 efx_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl);
222 efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
226 efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
229 efx_mdio_write(efx, mmd, TXC_BIST_CTL,
237 efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
241 bctl = efx_mdio_read(efx, mmd, TXC_BIST_CTL);
246 int count = efx_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane);
248 netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. "
252 count = efx_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane);
254 netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. "
261 netif_info(efx, hw, efx->net_dev, TXCNAME": BIST pass\n");
264 efx_mdio_write(efx, mmd, TXC_BIST_CTL, 0);
268 efx_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl);
273 static int txc_bist(struct efx_nic *efx)
275 return txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD);
280 static void txc_apply_defaults(struct efx_nic *efx)
290 efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, TXC_ATXPRE_NONE);
291 efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, TXC_ATXPRE_NONE);
294 efx_mdio_write(efx, MDIO_MMD_PHYXS,
296 efx_mdio_write(efx, MDIO_MMD_PHYXS,
302 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
304 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
306 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
308 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
312 mctrl = efx_mdio_read(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL);
316 efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL, mctrl);
319 txc_reset_logic(efx);
321 falcon_board(efx)->type->init_phy(efx);
324 static int txc43128_phy_probe(struct efx_nic *efx)
332 efx->phy_data = phy_data;
333 phy_data->phy_mode = efx->phy_mode;
335 efx->mdio.mmds = TXC_REQUIRED_DEVS;
336 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
338 efx->loopback_modes = TXC_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
344 static int txc43128_phy_init(struct efx_nic *efx)
348 rc = txc_reset_phy(efx);
352 rc = txc_bist(efx);
356 txc_apply_defaults(efx);
362 static void txc_glrgs_lane_power(struct efx_nic *efx, int mmd)
365 int ctl = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
367 if (!(efx->phy_mode & PHY_MODE_LOW_POWER))
372 efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, ctl);
376 static void txc_analog_lane_power(struct efx_nic *efx, int mmd)
382 int txctl = efx_mdio_read(efx, mmd, TXC_ALRGS_ATXCTL);
383 int rxctl = efx_mdio_read(efx, mmd, TXC_ALRGS_ARXCTL);
385 if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) {
393 efx_mdio_write(efx, mmd, TXC_ALRGS_ATXCTL, txctl);
394 efx_mdio_write(efx, mmd, TXC_ALRGS_ARXCTL, rxctl);
397 static void txc_set_power(struct efx_nic *efx)
400 efx_mdio_set_mmds_lpower(efx,
401 !!(efx->phy_mode & PHY_MODE_LOW_POWER),
406 txc_glrgs_lane_power(efx, MDIO_MMD_PCS);
407 txc_glrgs_lane_power(efx, MDIO_MMD_PHYXS);
410 txc_analog_lane_power(efx, MDIO_MMD_PMAPMD);
411 txc_analog_lane_power(efx, MDIO_MMD_PHYXS);
414 static void txc_reset_logic_mmd(struct efx_nic *efx, int mmd)
416 int val = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
420 efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, val);
422 val = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
428 netif_info(efx, hw, efx->net_dev,
434 static void txc_reset_logic(struct efx_nic *efx)
439 txc_reset_logic_mmd(efx, MDIO_MMD_PCS);
442 static bool txc43128_phy_read_link(struct efx_nic *efx)
444 return efx_mdio_links_ok(efx, TXC_REQUIRED_DEVS);
447 static int txc43128_phy_reconfigure(struct efx_nic *efx)
449 struct txc43128_data *phy_data = efx->phy_data;
450 enum efx_phy_mode mode_change = efx->phy_mode ^ phy_data->phy_mode;
451 bool loop_change = LOOPBACK_CHANGED(phy_data, efx, TXC_LOOPBACKS);
453 if (efx->phy_mode & mode_change & PHY_MODE_TX_DISABLED) {
454 txc_reset_phy(efx);
455 txc_apply_defaults(efx);
456 falcon_reset_xaui(efx);
460 efx_mdio_transmit_disable(efx);
461 efx_mdio_phy_reconfigure(efx);
463 txc_set_power(efx);
470 txc_reset_logic(efx);
472 phy_data->phy_mode = efx->phy_mode;
473 phy_data->loopback_mode = efx->loopback_mode;
478 static void txc43128_phy_fini(struct efx_nic *efx)
481 efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0);
484 static void txc43128_phy_remove(struct efx_nic *efx)
486 kfree(efx->phy_data);
487 efx->phy_data = NULL;
492 static bool txc43128_phy_poll(struct efx_nic *efx)
494 struct txc43128_data *data = efx->phy_data;
495 bool was_up = efx->link_state.up;
497 efx->link_state.up = txc43128_phy_read_link(efx);
498 efx->link_state.speed = 10000;
499 efx->link_state.fd = true;
500 efx->link_state.fc = efx->wanted_fc;
502 if (efx->link_state.up || (efx->loopback_mode != LOOPBACK_NONE)) {
508 txc_reset_logic(efx);
512 return efx->link_state.up != was_up;
519 static const char *txc43128_test_name(struct efx_nic *efx, unsigned int index)
526 static int txc43128_run_tests(struct efx_nic *efx, int *results, unsigned flags)
533 rc = txc_reset_phy(efx);
537 rc = txc_bist(efx);
538 txc_apply_defaults(efx);
543 static void txc43128_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
545 mdio45_ethtool_gset(&efx->mdio, ecmd);