1/**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2006-2011 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10/* 11 * Driver for Transwitch/Mysticom CX4 retimer 12 * see www.transwitch.com, part is TXC-43128 13 */ 14 15#include <linux/delay.h> 16#include <linux/slab.h> 17#include "efx.h" 18#include "mdio_10g.h" 19#include "phy.h" 20#include "nic.h" 21 22/* We expect these MMDs to be in the package */ 23#define TXC_REQUIRED_DEVS (MDIO_DEVS_PCS | \ 24 MDIO_DEVS_PMAPMD | \ 25 MDIO_DEVS_PHYXS) 26 27#define TXC_LOOPBACKS ((1 << LOOPBACK_PCS) | \ 28 (1 << LOOPBACK_PMAPMD) | \ 29 (1 << LOOPBACK_PHYXS_WS)) 30 31/************************************************************************** 32 * 33 * Compile-time config 34 * 35 ************************************************************************** 36 */ 37#define TXCNAME "TXC43128" 38/* Total length of time we'll wait for the PHY to come out of reset (ms) */ 39#define TXC_MAX_RESET_TIME 500 40/* Interval between checks (ms) */ 41#define TXC_RESET_WAIT 10 42/* How long to run BIST (us) */ 43#define TXC_BIST_DURATION 50 44 45/************************************************************************** 46 * 47 * Register definitions 48 * 49 ************************************************************************** 50 */ 51 52/* Command register */ 53#define TXC_GLRGS_GLCMD 0xc004 54/* Useful bits in command register */ 55/* Lane power-down */ 56#define TXC_GLCMD_L01PD_LBN 5 57#define TXC_GLCMD_L23PD_LBN 6 58/* Limited SW reset: preserves configuration but 59 * initiates a logic reset. Self-clearing */ 60#define TXC_GLCMD_LMTSWRST_LBN 14 61 62/* Signal Quality Control */ 63#define TXC_GLRGS_GSGQLCTL 0xc01a 64/* Enable bit */ 65#define TXC_GSGQLCT_SGQLEN_LBN 15 66/* Lane selection */ 67#define TXC_GSGQLCT_LNSL_LBN 13 68#define TXC_GSGQLCT_LNSL_WIDTH 2 69 70/* Analog TX control */ 71#define TXC_ALRGS_ATXCTL 0xc040 72/* Lane power-down */ 73#define TXC_ATXCTL_TXPD3_LBN 15 74#define TXC_ATXCTL_TXPD2_LBN 14 75#define TXC_ATXCTL_TXPD1_LBN 13 76#define TXC_ATXCTL_TXPD0_LBN 12 77 78/* Amplitude on lanes 0, 1 */ 79#define TXC_ALRGS_ATXAMP0 0xc041 80/* Amplitude on lanes 2, 3 */ 81#define TXC_ALRGS_ATXAMP1 0xc042 82/* Bit position of value for lane 0 (or 2) */ 83#define TXC_ATXAMP_LANE02_LBN 3 84/* Bit position of value for lane 1 (or 3) */ 85#define TXC_ATXAMP_LANE13_LBN 11 86 87#define TXC_ATXAMP_1280_mV 0 88#define TXC_ATXAMP_1200_mV 8 89#define TXC_ATXAMP_1120_mV 12 90#define TXC_ATXAMP_1060_mV 14 91#define TXC_ATXAMP_0820_mV 25 92#define TXC_ATXAMP_0720_mV 26 93#define TXC_ATXAMP_0580_mV 27 94#define TXC_ATXAMP_0440_mV 28 95 96#define TXC_ATXAMP_0820_BOTH \ 97 ((TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) \ 98 | (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN)) 99 100#define TXC_ATXAMP_DEFAULT 0x6060 /* From databook */ 101 102/* Preemphasis on lanes 0, 1 */ 103#define TXC_ALRGS_ATXPRE0 0xc043 104/* Preemphasis on lanes 2, 3 */ 105#define TXC_ALRGS_ATXPRE1 0xc044 106 107#define TXC_ATXPRE_NONE 0 108#define TXC_ATXPRE_DEFAULT 0x1010 /* From databook */ 109 110#define TXC_ALRGS_ARXCTL 0xc045 111/* Lane power-down */ 112#define TXC_ARXCTL_RXPD3_LBN 15 113#define TXC_ARXCTL_RXPD2_LBN 14 114#define TXC_ARXCTL_RXPD1_LBN 13 115#define TXC_ARXCTL_RXPD0_LBN 12 116 117/* Main control */ 118#define TXC_MRGS_CTL 0xc340 119/* Bits in main control */ 120#define TXC_MCTL_RESET_LBN 15 /* Self clear */ 121#define TXC_MCTL_TXLED_LBN 14 /* 1 to show align status */ 122#define TXC_MCTL_RXLED_LBN 13 /* 1 to show align status */ 123 124/* GPIO output */ 125#define TXC_GPIO_OUTPUT 0xc346 126#define TXC_GPIO_DIR 0xc348 127 128/* Vendor-specific BIST registers */ 129#define TXC_BIST_CTL 0xc280 130#define TXC_BIST_TXFRMCNT 0xc281 131#define TXC_BIST_RX0FRMCNT 0xc282 132#define TXC_BIST_RX1FRMCNT 0xc283 133#define TXC_BIST_RX2FRMCNT 0xc284 134#define TXC_BIST_RX3FRMCNT 0xc285 135#define TXC_BIST_RX0ERRCNT 0xc286 136#define TXC_BIST_RX1ERRCNT 0xc287 137#define TXC_BIST_RX2ERRCNT 0xc288 138#define TXC_BIST_RX3ERRCNT 0xc289 139 140/* BIST type (controls bit patter in test) */ 141#define TXC_BIST_CTRL_TYPE_LBN 10 142#define TXC_BIST_CTRL_TYPE_TSD 0 /* TranSwitch Deterministic */ 143#define TXC_BIST_CTRL_TYPE_CRP 1 /* CRPAT standard */ 144#define TXC_BIST_CTRL_TYPE_CJP 2 /* CJPAT standard */ 145#define TXC_BIST_CTRL_TYPE_TSR 3 /* TranSwitch pseudo-random */ 146/* Set this to 1 for 10 bit and 0 for 8 bit */ 147#define TXC_BIST_CTRL_B10EN_LBN 12 148/* Enable BIST (write 0 to disable) */ 149#define TXC_BIST_CTRL_ENAB_LBN 13 150/* Stop BIST (self-clears when stop complete) */ 151#define TXC_BIST_CTRL_STOP_LBN 14 152/* Start BIST (cleared by writing 1 to STOP) */ 153#define TXC_BIST_CTRL_STRT_LBN 15 154 155/* Mt. Diablo test configuration */ 156#define TXC_MTDIABLO_CTRL 0xc34f 157#define TXC_MTDIABLO_CTRL_PMA_LOOP_LBN 10 158 159struct txc43128_data { 160 unsigned long bug10934_timer; 161 enum efx_phy_mode phy_mode; 162 enum efx_loopback_mode loopback_mode; 163}; 164 165/* The PHY sometimes needs a reset to bring the link back up. So long as 166 * it reports link down, we reset it every 5 seconds. 167 */ 168#define BUG10934_RESET_INTERVAL (5 * HZ) 169 170/* Perform a reset that doesn't clear configuration changes */ 171static void txc_reset_logic(struct efx_nic *efx); 172 173/* Set the output value of a gpio */ 174void falcon_txc_set_gpio_val(struct efx_nic *efx, int pin, int on) 175{ 176 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_OUTPUT, 1 << pin, on); 177} 178 179/* Set up the GPIO direction register */ 180void falcon_txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir) 181{ 182 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_DIR, 1 << pin, dir); 183} 184 185/* Reset the PMA/PMD MMD. The documentation is explicit that this does a 186 * global reset (it's less clear what reset of other MMDs does).*/ 187static int txc_reset_phy(struct efx_nic *efx) 188{ 189 int rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PMAPMD, 190 TXC_MAX_RESET_TIME / TXC_RESET_WAIT, 191 TXC_RESET_WAIT); 192 if (rc < 0) 193 goto fail; 194 195 /* Check that all the MMDs we expect are present and responding. */ 196 rc = efx_mdio_check_mmds(efx, TXC_REQUIRED_DEVS); 197 if (rc < 0) 198 goto fail; 199 200 return 0; 201 202fail: 203 netif_err(efx, hw, efx->net_dev, TXCNAME ": reset timed out!\n"); 204 return rc; 205} 206 207/* Run a single BIST on one MMD */ 208static int txc_bist_one(struct efx_nic *efx, int mmd, int test) 209{ 210 int ctrl, bctl; 211 int lane; 212 int rc = 0; 213 214 /* Set PMA to test into loopback using Mt Diablo reg as per app note */ 215 ctrl = efx_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL); 216 ctrl |= (1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN); 217 efx_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl); 218 219 /* The BIST app. note lists these as 3 distinct steps. */ 220 /* Set the BIST type */ 221 bctl = (test << TXC_BIST_CTRL_TYPE_LBN); 222 efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl); 223 224 /* Set the BSTEN bit in the BIST Control register to enable */ 225 bctl |= (1 << TXC_BIST_CTRL_ENAB_LBN); 226 efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl); 227 228 /* Set the BSTRT bit in the BIST Control register */ 229 efx_mdio_write(efx, mmd, TXC_BIST_CTL, 230 bctl | (1 << TXC_BIST_CTRL_STRT_LBN)); 231 232 /* Wait. */ 233 udelay(TXC_BIST_DURATION); 234 235 /* Set the BSTOP bit in the BIST Control register */ 236 bctl |= (1 << TXC_BIST_CTRL_STOP_LBN); 237 efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl); 238 239 /* The STOP bit should go off when things have stopped */ 240 while (bctl & (1 << TXC_BIST_CTRL_STOP_LBN)) 241 bctl = efx_mdio_read(efx, mmd, TXC_BIST_CTL); 242 243 /* Check all the error counts are 0 and all the frame counts are 244 non-zero */ 245 for (lane = 0; lane < 4; lane++) { 246 int count = efx_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane); 247 if (count != 0) { 248 netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. " 249 "Lane %d had %d errs\n", lane, count); 250 rc = -EIO; 251 } 252 count = efx_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane); 253 if (count == 0) { 254 netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. " 255 "Lane %d got 0 frames\n", lane); 256 rc = -EIO; 257 } 258 } 259 260 if (rc == 0) 261 netif_info(efx, hw, efx->net_dev, TXCNAME": BIST pass\n"); 262 263 /* Disable BIST */ 264 efx_mdio_write(efx, mmd, TXC_BIST_CTL, 0); 265 266 /* Turn off loopback */ 267 ctrl &= ~(1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN); 268 efx_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl); 269 270 return rc; 271} 272 273static int txc_bist(struct efx_nic *efx) 274{ 275 return txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD); 276} 277 278/* Push the non-configurable defaults into the PHY. This must be 279 * done after every full reset */ 280static void txc_apply_defaults(struct efx_nic *efx) 281{ 282 int mctrl; 283 284 /* Turn amplitude down and preemphasis off on the host side 285 * (PHY<->MAC) as this is believed less likely to upset Falcon 286 * and no adverse effects have been noted. It probably also 287 * saves a picowatt or two */ 288 289 /* Turn off preemphasis */ 290 efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, TXC_ATXPRE_NONE); 291 efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, TXC_ATXPRE_NONE); 292 293 /* Turn down the amplitude */ 294 efx_mdio_write(efx, MDIO_MMD_PHYXS, 295 TXC_ALRGS_ATXAMP0, TXC_ATXAMP_0820_BOTH); 296 efx_mdio_write(efx, MDIO_MMD_PHYXS, 297 TXC_ALRGS_ATXAMP1, TXC_ATXAMP_0820_BOTH); 298 299 /* Set the line side amplitude and preemphasis to the databook 300 * defaults as an erratum causes them to be 0 on at least some 301 * PHY rev.s */ 302 efx_mdio_write(efx, MDIO_MMD_PMAPMD, 303 TXC_ALRGS_ATXPRE0, TXC_ATXPRE_DEFAULT); 304 efx_mdio_write(efx, MDIO_MMD_PMAPMD, 305 TXC_ALRGS_ATXPRE1, TXC_ATXPRE_DEFAULT); 306 efx_mdio_write(efx, MDIO_MMD_PMAPMD, 307 TXC_ALRGS_ATXAMP0, TXC_ATXAMP_DEFAULT); 308 efx_mdio_write(efx, MDIO_MMD_PMAPMD, 309 TXC_ALRGS_ATXAMP1, TXC_ATXAMP_DEFAULT); 310 311 /* Set up the LEDs */ 312 mctrl = efx_mdio_read(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL); 313 314 /* Set the Green and Red LEDs to their default modes */ 315 mctrl &= ~((1 << TXC_MCTL_TXLED_LBN) | (1 << TXC_MCTL_RXLED_LBN)); 316 efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL, mctrl); 317 318 /* Databook recommends doing this after configuration changes */ 319 txc_reset_logic(efx); 320 321 falcon_board(efx)->type->init_phy(efx); 322} 323 324static int txc43128_phy_probe(struct efx_nic *efx) 325{ 326 struct txc43128_data *phy_data; 327 328 /* Allocate phy private storage */ 329 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); 330 if (!phy_data) 331 return -ENOMEM; 332 efx->phy_data = phy_data; 333 phy_data->phy_mode = efx->phy_mode; 334 335 efx->mdio.mmds = TXC_REQUIRED_DEVS; 336 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 337 338 efx->loopback_modes = TXC_LOOPBACKS | FALCON_XMAC_LOOPBACKS; 339 340 return 0; 341} 342 343/* Initialisation entry point for this PHY driver */ 344static int txc43128_phy_init(struct efx_nic *efx) 345{ 346 int rc; 347 348 rc = txc_reset_phy(efx); 349 if (rc < 0) 350 return rc; 351 352 rc = txc_bist(efx); 353 if (rc < 0) 354 return rc; 355 356 txc_apply_defaults(efx); 357 358 return 0; 359} 360 361/* Set the lane power down state in the global registers */ 362static void txc_glrgs_lane_power(struct efx_nic *efx, int mmd) 363{ 364 int pd = (1 << TXC_GLCMD_L01PD_LBN) | (1 << TXC_GLCMD_L23PD_LBN); 365 int ctl = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD); 366 367 if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) 368 ctl &= ~pd; 369 else 370 ctl |= pd; 371 372 efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, ctl); 373} 374 375/* Set the lane power down state in the analog control registers */ 376static void txc_analog_lane_power(struct efx_nic *efx, int mmd) 377{ 378 int txpd = (1 << TXC_ATXCTL_TXPD3_LBN) | (1 << TXC_ATXCTL_TXPD2_LBN) 379 | (1 << TXC_ATXCTL_TXPD1_LBN) | (1 << TXC_ATXCTL_TXPD0_LBN); 380 int rxpd = (1 << TXC_ARXCTL_RXPD3_LBN) | (1 << TXC_ARXCTL_RXPD2_LBN) 381 | (1 << TXC_ARXCTL_RXPD1_LBN) | (1 << TXC_ARXCTL_RXPD0_LBN); 382 int txctl = efx_mdio_read(efx, mmd, TXC_ALRGS_ATXCTL); 383 int rxctl = efx_mdio_read(efx, mmd, TXC_ALRGS_ARXCTL); 384 385 if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) { 386 txctl &= ~txpd; 387 rxctl &= ~rxpd; 388 } else { 389 txctl |= txpd; 390 rxctl |= rxpd; 391 } 392 393 efx_mdio_write(efx, mmd, TXC_ALRGS_ATXCTL, txctl); 394 efx_mdio_write(efx, mmd, TXC_ALRGS_ARXCTL, rxctl); 395} 396 397static void txc_set_power(struct efx_nic *efx) 398{ 399 /* According to the data book, all the MMDs can do low power */ 400 efx_mdio_set_mmds_lpower(efx, 401 !!(efx->phy_mode & PHY_MODE_LOW_POWER), 402 TXC_REQUIRED_DEVS); 403 404 /* Global register bank is in PCS, PHY XS. These control the host 405 * side and line side settings respectively. */ 406 txc_glrgs_lane_power(efx, MDIO_MMD_PCS); 407 txc_glrgs_lane_power(efx, MDIO_MMD_PHYXS); 408 409 /* Analog register bank in PMA/PMD, PHY XS */ 410 txc_analog_lane_power(efx, MDIO_MMD_PMAPMD); 411 txc_analog_lane_power(efx, MDIO_MMD_PHYXS); 412} 413 414static void txc_reset_logic_mmd(struct efx_nic *efx, int mmd) 415{ 416 int val = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD); 417 int tries = 50; 418 419 val |= (1 << TXC_GLCMD_LMTSWRST_LBN); 420 efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, val); 421 while (tries--) { 422 val = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD); 423 if (!(val & (1 << TXC_GLCMD_LMTSWRST_LBN))) 424 break; 425 udelay(1); 426 } 427 if (!tries) 428 netif_info(efx, hw, efx->net_dev, 429 TXCNAME " Logic reset timed out!\n"); 430} 431 432/* Perform a logic reset. This preserves the configuration registers 433 * and is needed for some configuration changes to take effect */ 434static void txc_reset_logic(struct efx_nic *efx) 435{ 436 /* The data sheet claims we can do the logic reset on either the 437 * PCS or the PHYXS and the result is a reset of both host- and 438 * line-side logic. */ 439 txc_reset_logic_mmd(efx, MDIO_MMD_PCS); 440} 441 442static bool txc43128_phy_read_link(struct efx_nic *efx) 443{ 444 return efx_mdio_links_ok(efx, TXC_REQUIRED_DEVS); 445} 446 447static int txc43128_phy_reconfigure(struct efx_nic *efx) 448{ 449 struct txc43128_data *phy_data = efx->phy_data; 450 enum efx_phy_mode mode_change = efx->phy_mode ^ phy_data->phy_mode; 451 bool loop_change = LOOPBACK_CHANGED(phy_data, efx, TXC_LOOPBACKS); 452 453 if (efx->phy_mode & mode_change & PHY_MODE_TX_DISABLED) { 454 txc_reset_phy(efx); 455 txc_apply_defaults(efx); 456 falcon_reset_xaui(efx); 457 mode_change &= ~PHY_MODE_TX_DISABLED; 458 } 459 460 efx_mdio_transmit_disable(efx); 461 efx_mdio_phy_reconfigure(efx); 462 if (mode_change & PHY_MODE_LOW_POWER) 463 txc_set_power(efx); 464 465 /* The data sheet claims this is required after every reconfiguration 466 * (note at end of 7.1), but we mustn't do it when nothing changes as 467 * it glitches the link, and reconfigure gets called on link change, 468 * so we get an IRQ storm on link up. */ 469 if (loop_change || mode_change) 470 txc_reset_logic(efx); 471 472 phy_data->phy_mode = efx->phy_mode; 473 phy_data->loopback_mode = efx->loopback_mode; 474 475 return 0; 476} 477 478static void txc43128_phy_fini(struct efx_nic *efx) 479{ 480 /* Disable link events */ 481 efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0); 482} 483 484static void txc43128_phy_remove(struct efx_nic *efx) 485{ 486 kfree(efx->phy_data); 487 efx->phy_data = NULL; 488} 489 490/* Periodic callback: this exists mainly to poll link status as we 491 * don't use LASI interrupts */ 492static bool txc43128_phy_poll(struct efx_nic *efx) 493{ 494 struct txc43128_data *data = efx->phy_data; 495 bool was_up = efx->link_state.up; 496 497 efx->link_state.up = txc43128_phy_read_link(efx); 498 efx->link_state.speed = 10000; 499 efx->link_state.fd = true; 500 efx->link_state.fc = efx->wanted_fc; 501 502 if (efx->link_state.up || (efx->loopback_mode != LOOPBACK_NONE)) { 503 data->bug10934_timer = jiffies; 504 } else { 505 if (time_after_eq(jiffies, (data->bug10934_timer + 506 BUG10934_RESET_INTERVAL))) { 507 data->bug10934_timer = jiffies; 508 txc_reset_logic(efx); 509 } 510 } 511 512 return efx->link_state.up != was_up; 513} 514 515static const char *const txc43128_test_names[] = { 516 "bist" 517}; 518 519static const char *txc43128_test_name(struct efx_nic *efx, unsigned int index) 520{ 521 if (index < ARRAY_SIZE(txc43128_test_names)) 522 return txc43128_test_names[index]; 523 return NULL; 524} 525 526static int txc43128_run_tests(struct efx_nic *efx, int *results, unsigned flags) 527{ 528 int rc; 529 530 if (!(flags & ETH_TEST_FL_OFFLINE)) 531 return 0; 532 533 rc = txc_reset_phy(efx); 534 if (rc < 0) 535 return rc; 536 537 rc = txc_bist(efx); 538 txc_apply_defaults(efx); 539 results[0] = rc ? -1 : 1; 540 return rc; 541} 542 543static void txc43128_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) 544{ 545 mdio45_ethtool_gset(&efx->mdio, ecmd); 546} 547 548const struct efx_phy_operations falcon_txc_phy_ops = { 549 .probe = txc43128_phy_probe, 550 .init = txc43128_phy_init, 551 .reconfigure = txc43128_phy_reconfigure, 552 .poll = txc43128_phy_poll, 553 .fini = txc43128_phy_fini, 554 .remove = txc43128_phy_remove, 555 .get_settings = txc43128_get_settings, 556 .set_settings = efx_mdio_set_settings, 557 .test_alive = efx_mdio_test_alive, 558 .run_tests = txc43128_run_tests, 559 .test_name = txc43128_test_name, 560}; 561