Lines Matching refs:priv
225 struct scc_priv priv[2];
234 static void write_scc(struct scc_priv *priv, int reg, int val);
235 static void write_scc_data(struct scc_priv *priv, int val, int fast);
236 static int read_scc(struct scc_priv *priv, int reg);
237 static int read_scc_data(struct scc_priv *priv);
245 static inline void tx_on(struct scc_priv *priv);
246 static inline void rx_on(struct scc_priv *priv);
247 static inline void rx_off(struct scc_priv *priv);
248 static void start_timer(struct scc_priv *priv, int t, int r15);
253 static void rx_isr(struct scc_priv *priv);
254 static void special_condition(struct scc_priv *priv, int rc);
256 static void tx_isr(struct scc_priv *priv);
257 static void es_isr(struct scc_priv *priv);
258 static void tm_isr(struct scc_priv *priv);
293 if (info->priv[0].type == TYPE_TWIN)
295 write_scc(&info->priv[0], R9, FHWRES);
297 hw[info->priv[0].type].io_size);
457 struct scc_priv *priv;
491 priv = &info->priv[0];
492 priv->type = type;
493 priv->card_base = card_base;
494 priv->scc_cmd = scc_base + SCCA_CMD;
495 priv->scc_data = scc_base + SCCA_DATA;
496 priv->register_lock = &info->register_lock;
499 write_scc(priv, R9, FHWRES | MIE | NV);
502 write_scc(priv, R15, SHDLCE);
503 if (!read_scc(priv, R15)) {
508 write_scc_data(priv, 0, 0);
509 if (read_scc(priv, R0) & Tx_BUF_EMP) {
517 write_scc(priv, R15, 0);
530 write_scc(priv, R15, CTSIE);
531 write_scc(priv, R0, RES_EXT_INT);
532 write_scc(priv, R1, EXT_INT_ENAB);
548 write_scc(priv, R1, 0);
549 write_scc(priv, R15, 0);
550 write_scc(priv, R0, RES_EXT_INT);
563 priv = &info->priv[i];
564 priv->type = type;
565 priv->chip = chip;
566 priv->dev = dev;
567 priv->info = info;
568 priv->channel = i;
569 spin_lock_init(&priv->ring_lock);
570 priv->register_lock = &info->register_lock;
571 priv->card_base = card_base;
572 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
573 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
574 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
575 priv->tmr_ctrl = tmr_base + TMR_CTRL;
576 priv->tmr_mode = i ? 0xb0 : 0x70;
577 priv->param.pclk_hz = hw[type].pclk_hz;
578 priv->param.brg_tc = -1;
579 priv->param.clocks = TCTRxCP | RCRTxCP;
580 priv->param.persist = 256;
581 priv->param.dma = -1;
582 INIT_WORK(&priv->rx_work, rx_bh);
583 dev->ml_priv = priv;
611 if (info->priv[0].type == TYPE_TWIN)
613 write_scc(&info->priv[0], R9, FHWRES);
626 static void write_scc(struct scc_priv *priv, int reg, int val)
629 switch (priv->type) {
632 outb(reg, priv->scc_cmd);
633 outb(val, priv->scc_cmd);
637 outb_p(reg, priv->scc_cmd);
638 outb_p(val, priv->scc_cmd);
641 spin_lock_irqsave(priv->register_lock, flags);
642 outb_p(0, priv->card_base + PI_DREQ_MASK);
644 outb_p(reg, priv->scc_cmd);
645 outb_p(val, priv->scc_cmd);
646 outb(1, priv->card_base + PI_DREQ_MASK);
647 spin_unlock_irqrestore(priv->register_lock, flags);
653 static void write_scc_data(struct scc_priv *priv, int val, int fast)
656 switch (priv->type) {
658 outb(val, priv->scc_data);
661 outb_p(val, priv->scc_data);
665 outb_p(val, priv->scc_data);
667 spin_lock_irqsave(priv->register_lock, flags);
668 outb_p(0, priv->card_base + PI_DREQ_MASK);
669 outb_p(val, priv->scc_data);
670 outb(1, priv->card_base + PI_DREQ_MASK);
671 spin_unlock_irqrestore(priv->register_lock, flags);
678 static int read_scc(struct scc_priv *priv, int reg)
682 switch (priv->type) {
685 outb(reg, priv->scc_cmd);
686 return inb(priv->scc_cmd);
689 outb_p(reg, priv->scc_cmd);
690 return inb_p(priv->scc_cmd);
692 spin_lock_irqsave(priv->register_lock, flags);
693 outb_p(0, priv->card_base + PI_DREQ_MASK);
695 outb_p(reg, priv->scc_cmd);
696 rc = inb_p(priv->scc_cmd);
697 outb(1, priv->card_base + PI_DREQ_MASK);
698 spin_unlock_irqrestore(priv->register_lock, flags);
704 static int read_scc_data(struct scc_priv *priv)
708 switch (priv->type) {
710 return inb(priv->scc_data);
712 return inb_p(priv->scc_data);
714 spin_lock_irqsave(priv->register_lock, flags);
715 outb_p(0, priv->card_base + PI_DREQ_MASK);
716 rc = inb_p(priv->scc_data);
717 outb(1, priv->card_base + PI_DREQ_MASK);
718 spin_unlock_irqrestore(priv->register_lock, flags);
726 struct scc_priv *priv = dev->ml_priv;
727 struct scc_info *info = priv->info;
728 int card_base = priv->card_base;
739 if (priv->param.dma >= 0) {
740 if (request_dma(priv->param.dma, "dmascc")) {
746 clear_dma_ff(priv->param.dma);
752 priv->rx_ptr = 0;
753 priv->rx_over = 0;
754 priv->rx_head = priv->rx_tail = priv->rx_count = 0;
755 priv->state = IDLE;
756 priv->tx_head = priv->tx_tail = priv->tx_count = 0;
757 priv->tx_ptr = 0;
760 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
762 write_scc(priv, R4, SDLC | X1CLK);
764 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
766 write_scc(priv, R3, Rx8);
768 write_scc(priv, R5, Tx8);
770 write_scc(priv, R6, 0);
772 write_scc(priv, R7, FLAG);
773 switch (priv->chip) {
776 write_scc(priv, R15, SHDLCE);
778 write_scc(priv, R7, AUTOEOM);
779 write_scc(priv, R15, 0);
783 write_scc(priv, R15, SHDLCE);
803 if (priv->param.dma >= 0) {
804 if (priv->type == TYPE_TWIN)
805 write_scc(priv, R7, AUTOEOM | TXFIFOE);
807 write_scc(priv, R7, AUTOEOM);
809 write_scc(priv, R7, AUTOEOM | RXFIFOH);
811 write_scc(priv, R15, 0);
815 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
818 if (priv->param.brg_tc >= 0) {
820 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
821 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
824 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
826 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
829 write_scc(priv, R14, DTRREQ | BRSRC);
833 if (priv->type == TYPE_TWIN) {
836 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
839 write_scc(priv, R11, priv->param.clocks);
840 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
843 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
848 if (priv->type == TYPE_TWIN) {
851 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
856 priv->rr0 = read_scc(priv, R0);
858 write_scc(priv, R15, DCDIE);
868 struct scc_priv *priv = dev->ml_priv;
869 struct scc_info *info = priv->info;
870 int card_base = priv->card_base;
874 if (priv->type == TYPE_TWIN) {
877 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
882 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
883 if (priv->param.dma >= 0) {
884 if (priv->type == TYPE_TWIN)
886 free_dma(priv->param.dma);
897 struct scc_priv *priv = dev->ml_priv;
902 (ifr->ifr_data, &priv->param,
912 (&priv->param, ifr->ifr_data,
924 struct scc_priv *priv = dev->ml_priv;
932 i = priv->tx_head;
933 skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1);
934 priv->tx_len[i] = skb->len - 1;
938 spin_lock_irqsave(&priv->ring_lock, flags);
940 priv->tx_head = (i + 1) % NUM_TX_BUF;
941 priv->tx_count++;
946 if (priv->tx_count < NUM_TX_BUF)
950 if (priv->state == IDLE) {
952 priv->state = TX_HEAD;
953 priv->tx_start = jiffies;
954 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
955 write_scc(priv, R15, 0);
956 start_timer(priv, priv->param.txdelay, 0);
960 spin_unlock_irqrestore(&priv->ring_lock, flags);
975 static inline void tx_on(struct scc_priv *priv)
980 if (priv->param.dma >= 0) {
981 n = (priv->chip == Z85230) ? 3 : 1;
984 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
985 set_dma_addr(priv->param.dma,
986 (int) priv->tx_buf[priv->tx_tail] + n);
987 set_dma_count(priv->param.dma,
988 priv->tx_len[priv->tx_tail] - n);
991 write_scc(priv, R15, TxUIE);
993 if (priv->type == TYPE_TWIN)
994 outb((priv->param.dma ==
996 priv->card_base + TWIN_DMA_CFG);
998 write_scc(priv, R1,
1002 spin_lock_irqsave(priv->register_lock, flags);
1004 write_scc_data(priv,
1005 priv->tx_buf[priv->tx_tail][i], 1);
1006 enable_dma(priv->param.dma);
1007 spin_unlock_irqrestore(priv->register_lock, flags);
1009 write_scc(priv, R15, TxUIE);
1010 write_scc(priv, R1,
1012 tx_isr(priv);
1015 if (priv->chip == Z8530)
1016 write_scc(priv, R0, RES_EOM_L);
1020 static inline void rx_on(struct scc_priv *priv)
1025 while (read_scc(priv, R0) & Rx_CH_AV)
1026 read_scc_data(priv);
1027 priv->rx_over = 0;
1028 if (priv->param.dma >= 0) {
1031 set_dma_mode(priv->param.dma, DMA_MODE_READ);
1032 set_dma_addr(priv->param.dma,
1033 (int) priv->rx_buf[priv->rx_head]);
1034 set_dma_count(priv->param.dma, BUF_SIZE);
1036 enable_dma(priv->param.dma);
1038 if (priv->type == TYPE_TWIN) {
1039 outb((priv->param.dma ==
1041 priv->card_base + TWIN_DMA_CFG);
1044 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1048 priv->rx_ptr = 0;
1050 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1053 write_scc(priv, R0, ERR_RES);
1054 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1058 static inline void rx_off(struct scc_priv *priv)
1061 write_scc(priv, R3, Rx8);
1063 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1064 outb(0, priv->card_base + TWIN_DMA_CFG);
1066 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1068 if (priv->param.dma >= 0)
1069 disable_dma(priv->param.dma);
1073 static void start_timer(struct scc_priv *priv, int t, int r15)
1075 outb(priv->tmr_mode, priv->tmr_ctrl);
1077 tm_isr(priv);
1079 outb(t & 0xFF, priv->tmr_cnt);
1080 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1081 if (priv->type != TYPE_TWIN) {
1082 write_scc(priv, R15, r15 | CTSIE);
1083 priv->rr0 |= CTS;
1100 while ((is = read_scc(&info->priv[0], R3)) && i--) {
1102 rx_isr(&info->priv[0]);
1104 tx_isr(&info->priv[0]);
1106 es_isr(&info->priv[0]);
1108 rx_isr(&info->priv[1]);
1110 tx_isr(&info->priv[1]);
1112 es_isr(&info->priv[1]);
1114 write_scc(&info->priv[0], R0, RES_H_IUS);
1130 spin_lock(info->priv[0].register_lock);
1143 if (info->priv[0].type == TYPE_TWIN) {
1144 int is, card_base = info->priv[0].card_base;
1151 tm_isr(&info->priv[0]);
1154 tm_isr(&info->priv[1]);
1159 spin_unlock(info->priv[0].register_lock);
1164 static void rx_isr(struct scc_priv *priv)
1166 if (priv->param.dma >= 0) {
1168 special_condition(priv, read_scc(priv, R1));
1169 write_scc(priv, R0, ERR_RES);
1174 while (read_scc(priv, R0) & Rx_CH_AV) {
1175 rc = read_scc(priv, R1);
1176 if (priv->rx_ptr < BUF_SIZE)
1177 priv->rx_buf[priv->rx_head][priv->
1179 read_scc_data(priv);
1181 priv->rx_over = 2;
1182 read_scc_data(priv);
1184 special_condition(priv, rc);
1190 static void special_condition(struct scc_priv *priv, int rc)
1199 priv->rx_over = 1;
1200 if (priv->param.dma < 0)
1201 write_scc(priv, R0, ERR_RES);
1204 if (priv->param.dma >= 0) {
1206 cb = BUF_SIZE - get_dma_residue(priv->param.dma) -
1210 cb = priv->rx_ptr - 2;
1212 if (priv->rx_over) {
1214 priv->dev->stats.rx_errors++;
1215 if (priv->rx_over == 2)
1216 priv->dev->stats.rx_length_errors++;
1218 priv->dev->stats.rx_fifo_errors++;
1219 priv->rx_over = 0;
1223 priv->dev->stats.rx_errors++;
1224 priv->dev->stats.rx_crc_errors++;
1228 if (priv->rx_count < NUM_RX_BUF - 1) {
1230 priv->rx_len[priv->rx_head] = cb;
1231 priv->rx_head =
1232 (priv->rx_head +
1234 priv->rx_count++;
1235 schedule_work(&priv->rx_work);
1237 priv->dev->stats.rx_errors++;
1238 priv->dev->stats.rx_over_errors++;
1243 if (priv->param.dma >= 0) {
1245 set_dma_addr(priv->param.dma,
1246 (int) priv->rx_buf[priv->rx_head]);
1247 set_dma_count(priv->param.dma, BUF_SIZE);
1250 priv->rx_ptr = 0;
1258 struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
1259 int i = priv->rx_tail;
1265 spin_lock_irqsave(&priv->ring_lock, flags);
1266 while (priv->rx_count) {
1267 spin_unlock_irqrestore(&priv->ring_lock, flags);
1268 cb = priv->rx_len[i];
1273 priv->dev->stats.rx_dropped++;
1278 memcpy(&data[1], priv->rx_buf[i], cb);
1279 skb->protocol = ax25_type_trans(skb, priv->dev);
1281 priv->dev->stats.rx_packets++;
1282 priv->dev->stats.rx_bytes += cb;
1284 spin_lock_irqsave(&priv->ring_lock, flags);
1286 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1287 priv->rx_count--;
1289 spin_unlock_irqrestore(&priv->ring_lock, flags);
1293 static void tx_isr(struct scc_priv *priv)
1295 int i = priv->tx_tail, p = priv->tx_ptr;
1299 if (p == priv->tx_len[i]) {
1300 write_scc(priv, R0, RES_Tx_P);
1305 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1306 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1310 if (!priv->tx_ptr && p && priv->chip == Z8530)
1311 write_scc(priv, R0, RES_EOM_L);
1313 priv->tx_ptr = p;
1317 static void es_isr(struct scc_priv *priv)
1323 rr0 = read_scc(priv, R0);
1324 write_scc(priv, R0, RES_EXT_INT);
1325 drr0 = priv->rr0 ^ rr0;
1326 priv->rr0 = rr0;
1330 if (priv->state == TX_DATA) {
1332 i = priv->tx_tail;
1333 if (priv->param.dma >= 0) {
1334 disable_dma(priv->param.dma);
1336 res = get_dma_residue(priv->param.dma);
1339 res = priv->tx_len[i] - priv->tx_ptr;
1340 priv->tx_ptr = 0;
1343 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1344 outb(0, priv->card_base + TWIN_DMA_CFG);
1346 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1349 priv->dev->stats.tx_errors++;
1350 priv->dev->stats.tx_fifo_errors++;
1352 write_scc(priv, R0, RES_EXT_INT);
1353 write_scc(priv, R0, RES_EXT_INT);
1356 priv->dev->stats.tx_packets++;
1357 priv->dev->stats.tx_bytes += priv->tx_len[i];
1359 priv->tx_tail = (i + 1) % NUM_TX_BUF;
1360 priv->tx_count--;
1362 netif_wake_queue(priv->dev);
1365 write_scc(priv, R15, 0);
1366 if (priv->tx_count &&
1367 (jiffies - priv->tx_start) < priv->param.txtimeout) {
1368 priv->state = TX_PAUSE;
1369 start_timer(priv, priv->param.txpause, 0);
1371 priv->state = TX_TAIL;
1372 start_timer(priv, priv->param.txtail, 0);
1379 switch (priv->state) {
1382 priv->state = DCD_ON;
1383 write_scc(priv, R15, 0);
1384 start_timer(priv, priv->param.dcdon, 0);
1387 switch (priv->state) {
1389 rx_off(priv);
1390 priv->state = DCD_OFF;
1391 write_scc(priv, R15, 0);
1392 start_timer(priv, priv->param.dcdoff, 0);
1398 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1399 tm_isr(priv);
1404 static void tm_isr(struct scc_priv *priv)
1406 switch (priv->state) {
1409 tx_on(priv);
1410 priv->state = TX_DATA;
1413 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1414 priv->state = RTS_OFF;
1415 if (priv->type != TYPE_TWIN)
1416 write_scc(priv, R15, 0);
1417 start_timer(priv, priv->param.rtsoff, 0);
1420 write_scc(priv, R15, DCDIE);
1421 priv->rr0 = read_scc(priv, R0);
1422 if (priv->rr0 & DCD) {
1423 priv->dev->stats.collisions++;
1424 rx_on(priv);
1425 priv->state = RX_ON;
1427 priv->state = WAIT;
1428 start_timer(priv, priv->param.waittime, DCDIE);
1432 if (priv->tx_count) {
1433 priv->state = TX_HEAD;
1434 priv->tx_start = jiffies;
1435 write_scc(priv, R5,
1437 write_scc(priv, R15, 0);
1438 start_timer(priv, priv->param.txdelay, 0);
1440 priv->state = IDLE;
1441 if (priv->type != TYPE_TWIN)
1442 write_scc(priv, R15, DCDIE);
1447 write_scc(priv, R15, DCDIE);
1448 priv->rr0 = read_scc(priv, R0);
1449 if (priv->rr0 & DCD) {
1450 rx_on(priv);
1451 priv->state = RX_ON;
1453 priv->state = WAIT;
1454 start_timer(priv,
1455 random() / priv->param.persist *
1456 priv->param.slottime, DCDIE);