Lines Matching refs:mvi
30 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
33 struct mvs_phy *phy = &mvi->phy[i];
36 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
37 reg = mvs_read_port_vsr_data(mvi, i);
51 void set_phy_tuning(struct mvs_info *mvi, int phy_id,
70 if (mvi->pdev->revision == VANIR_A0_REV)
96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0);
97 tmp = mvs_read_port_vsr_data(mvi, phy_id);
102 mvs_write_port_vsr_data(mvi, phy_id, tmp);
105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1);
106 tmp = mvs_read_port_vsr_data(mvi, phy_id);
109 mvs_write_port_vsr_data(mvi, phy_id, tmp);
113 void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,
119 if ((mvi->pdev->revision == VANIR_A0_REV)
120 || (mvi->pdev->revision == VANIR_B0_REV))
130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);
131 tmp = mvs_read_port_vsr_data(mvi, phy_id);
139 mvs_write_port_vsr_data(mvi, phy_id, tmp);
145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
146 tmp = mvs_read_port_vsr_data(mvi, phy_id);
151 mvs_write_port_vsr_data(mvi, phy_id, tmp);
158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);
159 tmp = mvs_read_port_vsr_data(mvi, phy_id);
164 mvs_write_port_vsr_data(mvi, phy_id, tmp);
170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
171 tmp = mvs_read_port_vsr_data(mvi, phy_id);
176 mvs_write_port_vsr_data(mvi, phy_id, tmp);
180 void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)
183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
220 mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)
223 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);
225 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;
226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;
227 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;
230 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);
232 switch (mvi->pdev->revision) {
235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
236 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;
242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
243 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;
248 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);
251 mvi->hba_info_param.phy_rate[phy_id] = 0x2;
253 set_phy_tuning(mvi, phy_id,
254 mvi->hba_info_param.phy_tuning[phy_id]);
255 set_phy_ffe_tuning(mvi, phy_id,
256 mvi->hba_info_param.ffe_ctl[phy_id]);
257 set_phy_rate(mvi, phy_id,
258 mvi->hba_info_param.phy_rate[phy_id]);
261 static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
263 void __iomem *regs = mvi->regs;
271 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
276 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL);
277 tmp = mvs_read_port_cfg_data(mvi, phy_id);
278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000);
279 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000);
282 tmp = mvs_read_port_irq_stat(mvi, phy_id);
284 mvs_write_port_irq_stat(mvi, phy_id, tmp);
286 tmp = mvs_read_phy_ctl(mvi, phy_id);
288 mvs_write_phy_ctl(mvi, phy_id, tmp);
290 tmp = mvs_read_phy_ctl(mvi, phy_id);
297 tmp = mvs_read_phy_ctl(mvi, phy_id);
299 mvs_write_phy_ctl(mvi, phy_id, tmp);
303 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
306 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
307 tmp = mvs_read_port_vsr_data(mvi, phy_id);
308 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
311 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
316 revision = mvi->pdev->revision;
318 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
319 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
322 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);
323 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);
324 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
325 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);
328 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
329 tmp = mvs_read_port_vsr_data(mvi, phy_id);
331 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
334 static int __devinit mvs_94xx_init(struct mvs_info *mvi)
336 void __iomem *regs = mvi->regs;
341 revision = mvi->pdev->revision;
342 mvs_show_pcie_usage(mvi);
343 if (mvi->flags & MVF_FLAG_SOC) {
358 if (mvi->flags & MVF_FLAG_SOC) {
399 mvs_phy_hacks(mvi);
402 tmp = mvs_cr32(mvi, CMD_SAS_CTL1);
408 mvs_cw32(mvi, CMD_SAS_CTL1, tmp);
418 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
419 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
421 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
422 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
425 mw32(MVS_TX_LO, mvi->tx_dma);
426 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
429 mw32(MVS_RX_LO, mvi->rx_dma);
430 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
432 for (i = 0; i < mvi->chip->n_phy; i++) {
433 mvs_94xx_phy_disable(mvi, i);
435 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
436 cpu_to_le64(mvi->phy[i].dev_sas_addr));
438 mvs_94xx_enable_xmt(mvi, i);
439 mvs_94xx_config_reg_from_hba(mvi, i);
440 mvs_94xx_phy_enable(mvi, i);
442 mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD);
444 mvs_94xx_detect_porttype(mvi, i);
447 if (mvi->flags & MVF_FLAG_SOC) {
458 for (i = 0; i < mvi->chip->n_phy; i++) {
460 tmp = mvs_read_port_irq_stat(mvi, i);
462 mvs_write_port_irq_stat(mvi, i, tmp);
467 mvs_write_port_irq_mask(mvi, i, tmp);
470 mvs_update_phyinfo(mvi, i, 1);
513 tmp = mvs_cr32(mvi, CMD_LINK_TIMER);
515 mvs_cw32(mvi, CMD_LINK_TIMER, tmp);
519 mvs_cw32(mvi, CMD_PL_TIMER, tmp);
522 tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1);
524 mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp);
528 tmp = mvs_cr32(mvi, CMD_SL_MODE0);
532 mvs_cw32(mvi, CMD_SL_MODE0, tmp);
540 static int mvs_94xx_ioremap(struct mvs_info *mvi)
542 if (!mvs_ioremap(mvi, 2, -1)) {
543 mvi->regs_ex = mvi->regs + 0x10200;
544 mvi->regs += 0x20000;
545 if (mvi->id == 1)
546 mvi->regs += 0x4000;
552 static void mvs_94xx_iounmap(struct mvs_info *mvi)
554 if (mvi->regs) {
555 mvi->regs -= 0x20000;
556 if (mvi->id == 1)
557 mvi->regs -= 0x4000;
558 mvs_iounmap(mvi->regs);
562 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
564 void __iomem *regs = mvi->regs_ex;
577 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
579 void __iomem *regs = mvi->regs_ex;
593 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
595 void __iomem *regs = mvi->regs_ex;
597 if (!(mvi->flags & MVF_FLAG_SOC)) {
606 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
608 void __iomem *regs = mvi->regs;
610 if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
611 ((stat & IRQ_SAS_B) && mvi->id == 1)) {
614 spin_lock(&mvi->lock);
615 mvs_int_full(mvi);
616 spin_unlock(&mvi->lock);
621 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
624 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));
627 mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),
630 tmp = mvs_cr32(mvi,
636 void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
638 void __iomem *regs = mvi->regs;
668 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
671 void __iomem *regs = mvi->regs;
673 mvs_94xx_clear_srs_irq(mvi, 0, 1);
681 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi)
683 void __iomem *regs = mvi->regs;
695 device = mvs_find_dev_by_reg_set(mvi, i);
697 mvs_release_task(mvi, device->sas_device);
700 device = mvs_find_dev_by_reg_set(mvi, i+32);
702 mvs_release_task(mvi, device->sas_device);
710 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
712 void __iomem *regs = mvi->regs;
718 mvi->sata_reg_set &= ~bit(reg_set);
720 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
722 w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32));
729 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
732 void __iomem *regs = mvi->regs;
737 i = mv_ffc64(mvi->sata_reg_set);
739 mvi->sata_reg_set |= bit(i);
740 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
744 mvi->sata_reg_set |= bit(i);
745 w_reg_set_enable(i, (u32)mvi->sata_reg_set);
767 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
770 phy_st = mvs_read_phy_ctl(mvi, i);
776 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
783 mvs_write_port_cfg_addr(mvi, port_id,
785 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));
790 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
797 mvs_write_port_cfg_addr(mvi, port_id,
799 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));
801 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
833 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
836 struct mvs_phy *phy = &mvi->phy[i];
846 mvs_94xx_get_dev_identify_frame(mvi, i, id);
850 mvs_94xx_get_att_identify_frame(mvi, i, id);
858 mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
859 mvs_write_port_cfg_data(mvi, i, 0x04);
863 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
869 tmp = mvs_read_phy_ctl(mvi, phy_id);
876 mvs_write_phy_ctl(mvi, phy_id, tmp);
877 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);
880 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
883 void __iomem *regs = mvi->regs;
893 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
895 void __iomem *regs = mvi->regs_ex - 0x10200;
899 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
901 void __iomem *regs = mvi->regs_ex - 0x10200;
906 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
914 void __iomem *regs = mvi->regs_ex - 0x10200;
931 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
933 void __iomem *regs = mvi->regs_ex - 0x10200;
939 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
941 void __iomem *regs = mvi->regs_ex - 0x10200;
954 void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
966 if ((mvi->pdev->revision == VANIR_A0_REV) ||
967 (mvi->pdev->revision == VANIR_B0_REV))
969 mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1;
986 static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)
988 void __iomem *regs = mvi->regs;