1/* 2 * Marvell 88SE94xx hardware specific 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24*/ 25 26#include "mv_sas.h" 27#include "mv_94xx.h" 28#include "mv_chips.h" 29 30static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i) 31{ 32 u32 reg; 33 struct mvs_phy *phy = &mvi->phy[i]; 34 u32 phy_status; 35 36 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3); 37 reg = mvs_read_port_vsr_data(mvi, i); 38 phy_status = ((reg & 0x3f0000) >> 16) & 0xff; 39 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 40 switch (phy_status) { 41 case 0x10: 42 phy->phy_type |= PORT_TYPE_SAS; 43 break; 44 case 0x1d: 45 default: 46 phy->phy_type |= PORT_TYPE_SATA; 47 break; 48 } 49} 50 51void set_phy_tuning(struct mvs_info *mvi, int phy_id, 52 struct phy_tuning phy_tuning) 53{ 54 u32 tmp, setting_0 = 0, setting_1 = 0; 55 u8 i; 56 57 /* Remap information for B0 chip: 58 * 59 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) 60 * R0Dh -> R118h[31:16] (Generation 1 Setting 0) 61 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) 62 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) 63 * R10h -> R120h[15:0] (Generation 2 Setting 1) 64 * R11h -> R120h[31:16] (Generation 3 Setting 0) 65 * R12h -> R124h[15:0] (Generation 3 Setting 1) 66 * R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved)) 67 */ 68 69 /* A0 has a different set of registers */ 70 if (mvi->pdev->revision == VANIR_A0_REV) 71 return; 72 73 for (i = 0; i < 3; i++) { 74 /* loop 3 times, set Gen 1, Gen 2, Gen 3 */ 75 switch (i) { 76 case 0: 77 setting_0 = GENERATION_1_SETTING; 78 setting_1 = GENERATION_1_2_SETTING; 79 break; 80 case 1: 81 setting_0 = GENERATION_1_2_SETTING; 82 setting_1 = GENERATION_2_3_SETTING; 83 break; 84 case 2: 85 setting_0 = GENERATION_2_3_SETTING; 86 setting_1 = GENERATION_3_4_SETTING; 87 break; 88 } 89 90 /* Set: 91 * 92 * Transmitter Emphasis Enable 93 * Transmitter Emphasis Amplitude 94 * Transmitter Amplitude 95 */ 96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0); 97 tmp = mvs_read_port_vsr_data(mvi, phy_id); 98 tmp &= ~(0xFBE << 16); 99 tmp |= (((phy_tuning.trans_emp_en << 11) | 100 (phy_tuning.trans_emp_amp << 7) | 101 (phy_tuning.trans_amp << 1)) << 16); 102 mvs_write_port_vsr_data(mvi, phy_id, tmp); 103 104 /* Set Transmitter Amplitude Adjust */ 105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1); 106 tmp = mvs_read_port_vsr_data(mvi, phy_id); 107 tmp &= ~(0xC000); 108 tmp |= (phy_tuning.trans_amp_adj << 14); 109 mvs_write_port_vsr_data(mvi, phy_id, tmp); 110 } 111} 112 113void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id, 114 struct ffe_control ffe) 115{ 116 u32 tmp; 117 118 /* Don't run this if A0/B0 */ 119 if ((mvi->pdev->revision == VANIR_A0_REV) 120 || (mvi->pdev->revision == VANIR_B0_REV)) 121 return; 122 123 /* FFE Resistor and Capacitor */ 124 /* R10Ch DFE Resolution Control/Squelch and FFE Setting 125 * 126 * FFE_FORCE [7] 127 * FFE_RES_SEL [6:4] 128 * FFE_CAP_SEL [3:0] 129 */ 130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL); 131 tmp = mvs_read_port_vsr_data(mvi, phy_id); 132 tmp &= ~0xFF; 133 134 /* Read from HBA_Info_Page */ 135 tmp |= ((0x1 << 7) | 136 (ffe.ffe_rss_sel << 4) | 137 (ffe.ffe_cap_sel << 0)); 138 139 mvs_write_port_vsr_data(mvi, phy_id, tmp); 140 141 /* R064h PHY Mode Register 1 142 * 143 * DFE_DIS 18 144 */ 145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); 146 tmp = mvs_read_port_vsr_data(mvi, phy_id); 147 tmp &= ~0x40001; 148 /* Hard coding */ 149 /* No defines in HBA_Info_Page */ 150 tmp |= (0 << 18); 151 mvs_write_port_vsr_data(mvi, phy_id, tmp); 152 153 /* R110h DFE F0-F1 Coefficient Control/DFE Update Control 154 * 155 * DFE_UPDATE_EN [11:6] 156 * DFE_FX_FORCE [5:0] 157 */ 158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL); 159 tmp = mvs_read_port_vsr_data(mvi, phy_id); 160 tmp &= ~0xFFF; 161 /* Hard coding */ 162 /* No defines in HBA_Info_Page */ 163 tmp |= ((0x3F << 6) | (0x0 << 0)); 164 mvs_write_port_vsr_data(mvi, phy_id, tmp); 165 166 /* R1A0h Interface and Digital Reference Clock Control/Reserved_50h 167 * 168 * FFE_TRAIN_EN 3 169 */ 170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); 171 tmp = mvs_read_port_vsr_data(mvi, phy_id); 172 tmp &= ~0x8; 173 /* Hard coding */ 174 /* No defines in HBA_Info_Page */ 175 tmp |= (0 << 3); 176 mvs_write_port_vsr_data(mvi, phy_id, tmp); 177} 178 179/*Notice: this function must be called when phy is disabled*/ 180void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate) 181{ 182 union reg_phy_cfg phy_cfg, phy_cfg_tmp; 183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id); 185 phy_cfg.v = 0; 186 phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy; 187 phy_cfg.u.sas_support = 1; 188 phy_cfg.u.sata_support = 1; 189 phy_cfg.u.sata_host_mode = 1; 190 191 switch (rate) { 192 case 0x0: 193 /* support 1.5 Gbps */ 194 phy_cfg.u.speed_support = 1; 195 phy_cfg.u.snw_3_support = 0; 196 phy_cfg.u.tx_lnk_parity = 1; 197 phy_cfg.u.tx_spt_phs_lnk_rate = 0x30; 198 break; 199 case 0x1: 200 201 /* support 1.5, 3.0 Gbps */ 202 phy_cfg.u.speed_support = 3; 203 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c; 204 phy_cfg.u.tx_lgcl_lnk_rate = 0x08; 205 break; 206 case 0x2: 207 default: 208 /* support 1.5, 3.0, 6.0 Gbps */ 209 phy_cfg.u.speed_support = 7; 210 phy_cfg.u.snw_3_support = 1; 211 phy_cfg.u.tx_lnk_parity = 1; 212 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f; 213 phy_cfg.u.tx_lgcl_lnk_rate = 0x09; 214 break; 215 } 216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); 217} 218 219static void __devinit 220mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id) 221{ 222 u32 temp; 223 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); 224 if (temp == 0xFFFFFFFFL) { 225 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; 226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; 227 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; 228 } 229 230 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); 231 if (temp == 0xFFL) { 232 switch (mvi->pdev->revision) { 233 case VANIR_A0_REV: 234 case VANIR_B0_REV: 235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; 236 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; 237 break; 238 case VANIR_C0_REV: 239 case VANIR_C1_REV: 240 case VANIR_C2_REV: 241 default: 242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; 243 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; 244 break; 245 } 246 } 247 248 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); 249 if (temp == 0xFFL) 250 /*set default phy_rate = 6Gbps*/ 251 mvi->hba_info_param.phy_rate[phy_id] = 0x2; 252 253 set_phy_tuning(mvi, phy_id, 254 mvi->hba_info_param.phy_tuning[phy_id]); 255 set_phy_ffe_tuning(mvi, phy_id, 256 mvi->hba_info_param.ffe_ctl[phy_id]); 257 set_phy_rate(mvi, phy_id, 258 mvi->hba_info_param.phy_rate[phy_id]); 259} 260 261static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) 262{ 263 void __iomem *regs = mvi->regs; 264 u32 tmp; 265 266 tmp = mr32(MVS_PCS); 267 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); 268 mw32(MVS_PCS, tmp); 269} 270 271static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) 272{ 273 u32 tmp; 274 u32 delay = 5000; 275 if (hard == MVS_PHY_TUNE) { 276 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL); 277 tmp = mvs_read_port_cfg_data(mvi, phy_id); 278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); 279 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); 280 return; 281 } 282 tmp = mvs_read_port_irq_stat(mvi, phy_id); 283 tmp &= ~PHYEV_RDY_CH; 284 mvs_write_port_irq_stat(mvi, phy_id, tmp); 285 if (hard) { 286 tmp = mvs_read_phy_ctl(mvi, phy_id); 287 tmp |= PHY_RST_HARD; 288 mvs_write_phy_ctl(mvi, phy_id, tmp); 289 do { 290 tmp = mvs_read_phy_ctl(mvi, phy_id); 291 udelay(10); 292 delay--; 293 } while ((tmp & PHY_RST_HARD) && delay); 294 if (!delay) 295 mv_dprintk("phy hard reset failed.\n"); 296 } else { 297 tmp = mvs_read_phy_ctl(mvi, phy_id); 298 tmp |= PHY_RST; 299 mvs_write_phy_ctl(mvi, phy_id, tmp); 300 } 301} 302 303static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) 304{ 305 u32 tmp; 306 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 307 tmp = mvs_read_port_vsr_data(mvi, phy_id); 308 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); 309} 310 311static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) 312{ 313 u32 tmp; 314 u8 revision = 0; 315 316 revision = mvi->pdev->revision; 317 if (revision == VANIR_A0_REV) { 318 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); 319 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); 320 } 321 if (revision == VANIR_B0_REV) { 322 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL); 323 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006); 324 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); 325 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f); 326 } 327 328 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); 329 tmp = mvs_read_port_vsr_data(mvi, phy_id); 330 tmp |= bit(0); 331 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); 332} 333 334static int __devinit mvs_94xx_init(struct mvs_info *mvi) 335{ 336 void __iomem *regs = mvi->regs; 337 int i; 338 u32 tmp, cctl; 339 u8 revision; 340 341 revision = mvi->pdev->revision; 342 mvs_show_pcie_usage(mvi); 343 if (mvi->flags & MVF_FLAG_SOC) { 344 tmp = mr32(MVS_PHY_CTL); 345 tmp &= ~PCTL_PWR_OFF; 346 tmp |= PCTL_PHY_DSBL; 347 mw32(MVS_PHY_CTL, tmp); 348 } 349 350 /* Init Chip */ 351 /* make sure RST is set; HBA_RST /should/ have done that for us */ 352 cctl = mr32(MVS_CTL) & 0xFFFF; 353 if (cctl & CCTL_RST) 354 cctl &= ~CCTL_RST; 355 else 356 mw32_f(MVS_CTL, cctl | CCTL_RST); 357 358 if (mvi->flags & MVF_FLAG_SOC) { 359 tmp = mr32(MVS_PHY_CTL); 360 tmp &= ~PCTL_PWR_OFF; 361 tmp |= PCTL_COM_ON; 362 tmp &= ~PCTL_PHY_DSBL; 363 tmp |= PCTL_LINK_RST; 364 mw32(MVS_PHY_CTL, tmp); 365 msleep(100); 366 tmp &= ~PCTL_LINK_RST; 367 mw32(MVS_PHY_CTL, tmp); 368 msleep(100); 369 } 370 371 /* disable Multiplexing, enable phy implemented */ 372 mw32(MVS_PORTS_IMP, 0xFF); 373 374 if (revision == VANIR_A0_REV) { 375 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET); 376 mw32(MVS_PA_VSR_PORT, 0x00018080); 377 } 378 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2); 379 if (revision == VANIR_A0_REV || revision == VANIR_B0_REV) 380 /* set 6G/3G/1.5G, multiplexing, without SSC */ 381 mw32(MVS_PA_VSR_PORT, 0x0084d4fe); 382 else 383 /* set 6G/3G/1.5G, multiplexing, with and without SSC */ 384 mw32(MVS_PA_VSR_PORT, 0x0084fffe); 385 386 if (revision == VANIR_B0_REV) { 387 mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL); 388 mw32(MVS_PA_VSR_PORT, 0x08001006); 389 mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA); 390 mw32(MVS_PA_VSR_PORT, 0x0000705f); 391 } 392 393 /* reset control */ 394 mw32(MVS_PCS, 0); /* MVS_PCS */ 395 mw32(MVS_STP_REG_SET_0, 0); 396 mw32(MVS_STP_REG_SET_1, 0); 397 398 /* init phys */ 399 mvs_phy_hacks(mvi); 400 401 /* disable non data frame retry */ 402 tmp = mvs_cr32(mvi, CMD_SAS_CTL1); 403 if ((revision == VANIR_A0_REV) || 404 (revision == VANIR_B0_REV) || 405 (revision == VANIR_C0_REV)) { 406 tmp &= ~0xffff; 407 tmp |= 0x007f; 408 mvs_cw32(mvi, CMD_SAS_CTL1, tmp); 409 } 410 411 /* set LED blink when IO*/ 412 mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED); 413 tmp = mr32(MVS_PA_VSR_PORT); 414 tmp &= 0xFFFF00FF; 415 tmp |= 0x00003300; 416 mw32(MVS_PA_VSR_PORT, tmp); 417 418 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); 419 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); 420 421 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); 422 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); 423 424 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); 425 mw32(MVS_TX_LO, mvi->tx_dma); 426 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); 427 428 mw32(MVS_RX_CFG, MVS_RX_RING_SZ); 429 mw32(MVS_RX_LO, mvi->rx_dma); 430 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); 431 432 for (i = 0; i < mvi->chip->n_phy; i++) { 433 mvs_94xx_phy_disable(mvi, i); 434 /* set phy local SAS address */ 435 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4, 436 cpu_to_le64(mvi->phy[i].dev_sas_addr)); 437 438 mvs_94xx_enable_xmt(mvi, i); 439 mvs_94xx_config_reg_from_hba(mvi, i); 440 mvs_94xx_phy_enable(mvi, i); 441 442 mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD); 443 msleep(500); 444 mvs_94xx_detect_porttype(mvi, i); 445 } 446 447 if (mvi->flags & MVF_FLAG_SOC) { 448 /* set select registers */ 449 writel(0x0E008000, regs + 0x000); 450 writel(0x59000008, regs + 0x004); 451 writel(0x20, regs + 0x008); 452 writel(0x20, regs + 0x00c); 453 writel(0x20, regs + 0x010); 454 writel(0x20, regs + 0x014); 455 writel(0x20, regs + 0x018); 456 writel(0x20, regs + 0x01c); 457 } 458 for (i = 0; i < mvi->chip->n_phy; i++) { 459 /* clear phy int status */ 460 tmp = mvs_read_port_irq_stat(mvi, i); 461 tmp &= ~PHYEV_SIG_FIS; 462 mvs_write_port_irq_stat(mvi, i, tmp); 463 464 /* set phy int mask */ 465 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | 466 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ; 467 mvs_write_port_irq_mask(mvi, i, tmp); 468 469 msleep(100); 470 mvs_update_phyinfo(mvi, i, 1); 471 } 472 473 /* little endian for open address and command table, etc. */ 474 cctl = mr32(MVS_CTL); 475 cctl |= CCTL_ENDIAN_CMD; 476 cctl &= ~CCTL_ENDIAN_OPEN; 477 cctl |= CCTL_ENDIAN_RSP; 478 mw32_f(MVS_CTL, cctl); 479 480 /* reset CMD queue */ 481 tmp = mr32(MVS_PCS); 482 tmp |= PCS_CMD_RST; 483 tmp &= ~PCS_SELF_CLEAR; 484 mw32(MVS_PCS, tmp); 485 /* 486 * the max count is 0x1ff, while our max slot is 0x200, 487 * it will make count 0. 488 */ 489 tmp = 0; 490 if (MVS_CHIP_SLOT_SZ > 0x1ff) 491 mw32(MVS_INT_COAL, 0x1ff | COAL_EN); 492 else 493 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN); 494 495 /* default interrupt coalescing time is 128us */ 496 tmp = 0x10000 | interrupt_coalescing; 497 mw32(MVS_INT_COAL_TMOUT, tmp); 498 499 /* ladies and gentlemen, start your engines */ 500 mw32(MVS_TX_CFG, 0); 501 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); 502 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); 503 /* enable CMD/CMPL_Q/RESP mode */ 504 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN | 505 PCS_CMD_EN | PCS_CMD_STOP_ERR); 506 507 /* enable completion queue interrupt */ 508 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | 509 CINT_DMA_PCIE | CINT_NON_SPEC_NCQ_ERROR); 510 tmp |= CINT_PHY_MASK; 511 mw32(MVS_INT_MASK, tmp); 512 513 tmp = mvs_cr32(mvi, CMD_LINK_TIMER); 514 tmp |= 0xFFFF0000; 515 mvs_cw32(mvi, CMD_LINK_TIMER, tmp); 516 517 /* tune STP performance */ 518 tmp = 0x003F003F; 519 mvs_cw32(mvi, CMD_PL_TIMER, tmp); 520 521 /* This can improve expander large block size seq write performance */ 522 tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1); 523 tmp |= 0xFFFF007F; 524 mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp); 525 526 /* change the connection open-close behavior (bit 9) 527 * set bit8 to 1 for performance tuning */ 528 tmp = mvs_cr32(mvi, CMD_SL_MODE0); 529 tmp |= 0x00000300; 530 /* set bit0 to 0 to enable retry for no_dest reject case */ 531 tmp &= 0xFFFFFFFE; 532 mvs_cw32(mvi, CMD_SL_MODE0, tmp); 533 534 /* Enable SRS interrupt */ 535 mw32(MVS_INT_MASK_SRS_0, 0xFFFF); 536 537 return 0; 538} 539 540static int mvs_94xx_ioremap(struct mvs_info *mvi) 541{ 542 if (!mvs_ioremap(mvi, 2, -1)) { 543 mvi->regs_ex = mvi->regs + 0x10200; 544 mvi->regs += 0x20000; 545 if (mvi->id == 1) 546 mvi->regs += 0x4000; 547 return 0; 548 } 549 return -1; 550} 551 552static void mvs_94xx_iounmap(struct mvs_info *mvi) 553{ 554 if (mvi->regs) { 555 mvi->regs -= 0x20000; 556 if (mvi->id == 1) 557 mvi->regs -= 0x4000; 558 mvs_iounmap(mvi->regs); 559 } 560} 561 562static void mvs_94xx_interrupt_enable(struct mvs_info *mvi) 563{ 564 void __iomem *regs = mvi->regs_ex; 565 u32 tmp; 566 567 tmp = mr32(MVS_GBL_CTL); 568 tmp |= (IRQ_SAS_A | IRQ_SAS_B); 569 mw32(MVS_GBL_INT_STAT, tmp); 570 writel(tmp, regs + 0x0C); 571 writel(tmp, regs + 0x10); 572 writel(tmp, regs + 0x14); 573 writel(tmp, regs + 0x18); 574 mw32(MVS_GBL_CTL, tmp); 575} 576 577static void mvs_94xx_interrupt_disable(struct mvs_info *mvi) 578{ 579 void __iomem *regs = mvi->regs_ex; 580 u32 tmp; 581 582 tmp = mr32(MVS_GBL_CTL); 583 584 tmp &= ~(IRQ_SAS_A | IRQ_SAS_B); 585 mw32(MVS_GBL_INT_STAT, tmp); 586 writel(tmp, regs + 0x0C); 587 writel(tmp, regs + 0x10); 588 writel(tmp, regs + 0x14); 589 writel(tmp, regs + 0x18); 590 mw32(MVS_GBL_CTL, tmp); 591} 592 593static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq) 594{ 595 void __iomem *regs = mvi->regs_ex; 596 u32 stat = 0; 597 if (!(mvi->flags & MVF_FLAG_SOC)) { 598 stat = mr32(MVS_GBL_INT_STAT); 599 600 if (!(stat & (IRQ_SAS_A | IRQ_SAS_B))) 601 return 0; 602 } 603 return stat; 604} 605 606static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat) 607{ 608 void __iomem *regs = mvi->regs; 609 610 if (((stat & IRQ_SAS_A) && mvi->id == 0) || 611 ((stat & IRQ_SAS_B) && mvi->id == 1)) { 612 mw32_f(MVS_INT_STAT, CINT_DONE); 613 614 spin_lock(&mvi->lock); 615 mvs_int_full(mvi); 616 spin_unlock(&mvi->lock); 617 } 618 return IRQ_HANDLED; 619} 620 621static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx) 622{ 623 u32 tmp; 624 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3)); 625 if (tmp && 1 << (slot_idx % 32)) { 626 mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx); 627 mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3), 628 1 << (slot_idx % 32)); 629 do { 630 tmp = mvs_cr32(mvi, 631 MVS_COMMAND_ACTIVE + (slot_idx >> 3)); 632 } while (tmp & 1 << (slot_idx % 32)); 633 } 634} 635 636void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) 637{ 638 void __iomem *regs = mvi->regs; 639 u32 tmp; 640 641 if (clear_all) { 642 tmp = mr32(MVS_INT_STAT_SRS_0); 643 if (tmp) { 644 mv_dprintk("check SRS 0 %08X.\n", tmp); 645 mw32(MVS_INT_STAT_SRS_0, tmp); 646 } 647 tmp = mr32(MVS_INT_STAT_SRS_1); 648 if (tmp) { 649 mv_dprintk("check SRS 1 %08X.\n", tmp); 650 mw32(MVS_INT_STAT_SRS_1, tmp); 651 } 652 } else { 653 if (reg_set > 31) 654 tmp = mr32(MVS_INT_STAT_SRS_1); 655 else 656 tmp = mr32(MVS_INT_STAT_SRS_0); 657 658 if (tmp & (1 << (reg_set % 32))) { 659 mv_dprintk("register set 0x%x was stopped.\n", reg_set); 660 if (reg_set > 31) 661 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32)); 662 else 663 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); 664 } 665 } 666} 667 668static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, 669 u32 tfs) 670{ 671 void __iomem *regs = mvi->regs; 672 u32 tmp; 673 mvs_94xx_clear_srs_irq(mvi, 0, 1); 674 675 tmp = mr32(MVS_INT_STAT); 676 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP); 677 tmp = mr32(MVS_PCS) | 0xFF00; 678 mw32(MVS_PCS, tmp); 679} 680 681static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi) 682{ 683 void __iomem *regs = mvi->regs; 684 u32 err_0, err_1; 685 u8 i; 686 struct mvs_device *device; 687 688 err_0 = mr32(MVS_NON_NCQ_ERR_0); 689 err_1 = mr32(MVS_NON_NCQ_ERR_1); 690 691 mv_dprintk("non specific ncq error err_0:%x,err_1:%x.\n", 692 err_0, err_1); 693 for (i = 0; i < 32; i++) { 694 if (err_0 & bit(i)) { 695 device = mvs_find_dev_by_reg_set(mvi, i); 696 if (device) 697 mvs_release_task(mvi, device->sas_device); 698 } 699 if (err_1 & bit(i)) { 700 device = mvs_find_dev_by_reg_set(mvi, i+32); 701 if (device) 702 mvs_release_task(mvi, device->sas_device); 703 } 704 } 705 706 mw32(MVS_NON_NCQ_ERR_0, err_0); 707 mw32(MVS_NON_NCQ_ERR_1, err_1); 708} 709 710static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) 711{ 712 void __iomem *regs = mvi->regs; 713 u8 reg_set = *tfs; 714 715 if (*tfs == MVS_ID_NOT_MAPPED) 716 return; 717 718 mvi->sata_reg_set &= ~bit(reg_set); 719 if (reg_set < 32) 720 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); 721 else 722 w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32)); 723 724 *tfs = MVS_ID_NOT_MAPPED; 725 726 return; 727} 728 729static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) 730{ 731 int i; 732 void __iomem *regs = mvi->regs; 733 734 if (*tfs != MVS_ID_NOT_MAPPED) 735 return 0; 736 737 i = mv_ffc64(mvi->sata_reg_set); 738 if (i >= 32) { 739 mvi->sata_reg_set |= bit(i); 740 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32)); 741 *tfs = i; 742 return 0; 743 } else if (i >= 0) { 744 mvi->sata_reg_set |= bit(i); 745 w_reg_set_enable(i, (u32)mvi->sata_reg_set); 746 *tfs = i; 747 return 0; 748 } 749 return MVS_ID_NOT_MAPPED; 750} 751 752static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd) 753{ 754 int i; 755 struct scatterlist *sg; 756 struct mvs_prd *buf_prd = prd; 757 struct mvs_prd_imt im_len; 758 *(u32 *)&im_len = 0; 759 for_each_sg(scatter, sg, nr, i) { 760 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 761 im_len.len = sg_dma_len(sg); 762 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len); 763 buf_prd++; 764 } 765} 766 767static int mvs_94xx_oob_done(struct mvs_info *mvi, int i) 768{ 769 u32 phy_st; 770 phy_st = mvs_read_phy_ctl(mvi, i); 771 if (phy_st & PHY_READY_MASK) 772 return 1; 773 return 0; 774} 775 776static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id, 777 struct sas_identify_frame *id) 778{ 779 int i; 780 u32 id_frame[7]; 781 782 for (i = 0; i < 7; i++) { 783 mvs_write_port_cfg_addr(mvi, port_id, 784 CONFIG_ID_FRAME0 + i * 4); 785 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id)); 786 } 787 memcpy(id, id_frame, 28); 788} 789 790static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id, 791 struct sas_identify_frame *id) 792{ 793 int i; 794 u32 id_frame[7]; 795 796 for (i = 0; i < 7; i++) { 797 mvs_write_port_cfg_addr(mvi, port_id, 798 CONFIG_ATT_ID_FRAME0 + i * 4); 799 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id)); 800 mv_dprintk("94xx phy %d atta frame %d %x.\n", 801 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]); 802 } 803 memcpy(id, id_frame, 28); 804} 805 806static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id) 807{ 808 u32 att_dev_info = 0; 809 810 att_dev_info |= id->dev_type; 811 if (id->stp_iport) 812 att_dev_info |= PORT_DEV_STP_INIT; 813 if (id->smp_iport) 814 att_dev_info |= PORT_DEV_SMP_INIT; 815 if (id->ssp_iport) 816 att_dev_info |= PORT_DEV_SSP_INIT; 817 if (id->stp_tport) 818 att_dev_info |= PORT_DEV_STP_TRGT; 819 if (id->smp_tport) 820 att_dev_info |= PORT_DEV_SMP_TRGT; 821 if (id->ssp_tport) 822 att_dev_info |= PORT_DEV_SSP_TRGT; 823 824 att_dev_info |= (u32)id->phy_id<<24; 825 return att_dev_info; 826} 827 828static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id) 829{ 830 return mvs_94xx_make_dev_info(id); 831} 832 833static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i, 834 struct sas_identify_frame *id) 835{ 836 struct mvs_phy *phy = &mvi->phy[i]; 837 struct asd_sas_phy *sas_phy = &phy->sas_phy; 838 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status); 839 sas_phy->linkrate = 840 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 841 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET; 842 sas_phy->linkrate += 0x8; 843 mv_dprintk("get link rate is %d\n", sas_phy->linkrate); 844 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 845 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 846 mvs_94xx_get_dev_identify_frame(mvi, i, id); 847 phy->dev_info = mvs_94xx_make_dev_info(id); 848 849 if (phy->phy_type & PORT_TYPE_SAS) { 850 mvs_94xx_get_att_identify_frame(mvi, i, id); 851 phy->att_dev_info = mvs_94xx_make_att_info(id); 852 phy->att_dev_sas_addr = *(u64 *)id->sas_addr; 853 } else { 854 phy->att_dev_info = PORT_DEV_STP_TRGT | 1; 855 } 856 857 /* enable spin up bit */ 858 mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT); 859 mvs_write_port_cfg_data(mvi, i, 0x04); 860 861} 862 863void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, 864 struct sas_phy_linkrates *rates) 865{ 866 u32 lrmax = 0; 867 u32 tmp; 868 869 tmp = mvs_read_phy_ctl(mvi, phy_id); 870 lrmax = (rates->maximum_linkrate - SAS_LINK_RATE_1_5_GBPS) << 12; 871 872 if (lrmax) { 873 tmp &= ~(0x3 << 12); 874 tmp |= lrmax; 875 } 876 mvs_write_phy_ctl(mvi, phy_id, tmp); 877 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD); 878} 879 880static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi) 881{ 882 u32 tmp; 883 void __iomem *regs = mvi->regs; 884 tmp = mr32(MVS_STP_REG_SET_0); 885 mw32(MVS_STP_REG_SET_0, 0); 886 mw32(MVS_STP_REG_SET_0, tmp); 887 tmp = mr32(MVS_STP_REG_SET_1); 888 mw32(MVS_STP_REG_SET_1, 0); 889 mw32(MVS_STP_REG_SET_1, tmp); 890} 891 892 893u32 mvs_94xx_spi_read_data(struct mvs_info *mvi) 894{ 895 void __iomem *regs = mvi->regs_ex - 0x10200; 896 return mr32(SPI_RD_DATA_REG_94XX); 897} 898 899void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data) 900{ 901 void __iomem *regs = mvi->regs_ex - 0x10200; 902 mw32(SPI_RD_DATA_REG_94XX, data); 903} 904 905 906int mvs_94xx_spi_buildcmd(struct mvs_info *mvi, 907 u32 *dwCmd, 908 u8 cmd, 909 u8 read, 910 u8 length, 911 u32 addr 912 ) 913{ 914 void __iomem *regs = mvi->regs_ex - 0x10200; 915 u32 dwTmp; 916 917 dwTmp = ((u32)cmd << 8) | ((u32)length << 4); 918 if (read) 919 dwTmp |= SPI_CTRL_READ_94XX; 920 921 if (addr != MV_MAX_U32) { 922 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL)); 923 dwTmp |= SPI_ADDR_VLD_94XX; 924 } 925 926 *dwCmd = dwTmp; 927 return 0; 928} 929 930 931int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) 932{ 933 void __iomem *regs = mvi->regs_ex - 0x10200; 934 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX); 935 936 return 0; 937} 938 939int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) 940{ 941 void __iomem *regs = mvi->regs_ex - 0x10200; 942 u32 i, dwTmp; 943 944 for (i = 0; i < timeout; i++) { 945 dwTmp = mr32(SPI_CTRL_REG_94XX); 946 if (!(dwTmp & SPI_CTRL_SpiStart_94XX)) 947 return 0; 948 msleep(10); 949 } 950 951 return -1; 952} 953 954void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask, 955 int buf_len, int from, void *prd) 956{ 957 int i; 958 struct mvs_prd *buf_prd = prd; 959 dma_addr_t buf_dma; 960 struct mvs_prd_imt im_len; 961 962 *(u32 *)&im_len = 0; 963 buf_prd += from; 964 965#define PRD_CHAINED_ENTRY 0x01 966 if ((mvi->pdev->revision == VANIR_A0_REV) || 967 (mvi->pdev->revision == VANIR_B0_REV)) 968 buf_dma = (phy_mask <= 0x08) ? 969 mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1; 970 else 971 return; 972 973 for (i = from; i < MAX_SG_ENTRY; i++, ++buf_prd) { 974 if (i == MAX_SG_ENTRY - 1) { 975 buf_prd->addr = cpu_to_le64(virt_to_phys(buf_prd - 1)); 976 im_len.len = 2; 977 im_len.misc_ctl = PRD_CHAINED_ENTRY; 978 } else { 979 buf_prd->addr = cpu_to_le64(buf_dma); 980 im_len.len = buf_len; 981 } 982 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len); 983 } 984} 985 986static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time) 987{ 988 void __iomem *regs = mvi->regs; 989 u32 tmp = 0; 990 /* 991 * the max count is 0x1ff, while our max slot is 0x200, 992 * it will make count 0. 993 */ 994 if (time == 0) { 995 mw32(MVS_INT_COAL, 0); 996 mw32(MVS_INT_COAL_TMOUT, 0x10000); 997 } else { 998 if (MVS_CHIP_SLOT_SZ > 0x1ff) 999 mw32(MVS_INT_COAL, 0x1ff|COAL_EN); 1000 else 1001 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN); 1002 1003 tmp = 0x10000 | time; 1004 mw32(MVS_INT_COAL_TMOUT, tmp); 1005 } 1006 1007} 1008 1009const struct mvs_dispatch mvs_94xx_dispatch = { 1010 "mv94xx", 1011 mvs_94xx_init, 1012 NULL, 1013 mvs_94xx_ioremap, 1014 mvs_94xx_iounmap, 1015 mvs_94xx_isr, 1016 mvs_94xx_isr_status, 1017 mvs_94xx_interrupt_enable, 1018 mvs_94xx_interrupt_disable, 1019 mvs_read_phy_ctl, 1020 mvs_write_phy_ctl, 1021 mvs_read_port_cfg_data, 1022 mvs_write_port_cfg_data, 1023 mvs_write_port_cfg_addr, 1024 mvs_read_port_vsr_data, 1025 mvs_write_port_vsr_data, 1026 mvs_write_port_vsr_addr, 1027 mvs_read_port_irq_stat, 1028 mvs_write_port_irq_stat, 1029 mvs_read_port_irq_mask, 1030 mvs_write_port_irq_mask, 1031 mvs_94xx_command_active, 1032 mvs_94xx_clear_srs_irq, 1033 mvs_94xx_issue_stop, 1034 mvs_start_delivery, 1035 mvs_rx_update, 1036 mvs_int_full, 1037 mvs_94xx_assign_reg_set, 1038 mvs_94xx_free_reg_set, 1039 mvs_get_prd_size, 1040 mvs_get_prd_count, 1041 mvs_94xx_make_prd, 1042 mvs_94xx_detect_porttype, 1043 mvs_94xx_oob_done, 1044 mvs_94xx_fix_phy_info, 1045 NULL, 1046 mvs_94xx_phy_set_link_rate, 1047 mvs_hw_max_link_rate, 1048 mvs_94xx_phy_disable, 1049 mvs_94xx_phy_enable, 1050 mvs_94xx_phy_reset, 1051 NULL, 1052 mvs_94xx_clear_active_cmds, 1053 mvs_94xx_spi_read_data, 1054 mvs_94xx_spi_write_data, 1055 mvs_94xx_spi_buildcmd, 1056 mvs_94xx_spi_issuecmd, 1057 mvs_94xx_spi_waitdataready, 1058 mvs_94xx_fix_dma, 1059 mvs_94xx_tune_interrupt, 1060 mvs_94xx_non_spec_ncq_error, 1061}; 1062 1063