Cross Reference: /drivers/usb/host/alchemy-common.c

Lines Matching refs:base
5  *	    area. Au1550 has OHCI on different base address. No need to handle
95 static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
99 	r = __raw_readl(base + USB_DWC_CTRL2);
100 	s = __raw_readl(base + USB_DWC_CTRL3);
109 		__raw_writel(r, base + USB_DWC_CTRL2);
115 		__raw_writel(r, base + USB_DWC_CTRL2);
120 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
125 		__raw_writel(1, base + USB_DWC_CTRL7);  /* start OHCI clock */
128 		r = __raw_readl(base + USB_DWC_CTRL3);	/* enable OHCI block */
131 		__raw_writel(r, base + USB_DWC_CTRL3);
134 		__au1300_usb_phyctl(base, enable);	/* power up the PHYs */
136 		r = __raw_readl(base + USB_INT_ENABLE);
138 		__raw_writel(r, base + USB_INT_ENABLE);
142 		__raw_writel(0, base + USB_DWC_CTRL7);
145 		r = __raw_readl(base + USB_INT_ENABLE);
147 		__raw_writel(r, base + USB_INT_ENABLE);
150 		r = __raw_readl(base + USB_DWC_CTRL3);
153 		__raw_writel(r, base + USB_DWC_CTRL3);
156 		__au1300_usb_phyctl(base, enable);
160 static inline void __au1300_ehci_control(void __iomem *base, int enable)
165 		r = __raw_readl(base + USB_DWC_CTRL3);
167 		__raw_writel(r, base + USB_DWC_CTRL3);
170 		r = __raw_readl(base + USB_DWC_CTRL1);
172 		__raw_writel(r, base + USB_DWC_CTRL1);
175 		__au1300_usb_phyctl(base, enable);
177 		r = __raw_readl(base + USB_INT_ENABLE);
179 		__raw_writel(r, base + USB_INT_ENABLE);
182 		r = __raw_readl(base + USB_INT_ENABLE);
184 		__raw_writel(r, base + USB_INT_ENABLE);
187 		r = __raw_readl(base + USB_DWC_CTRL1);
189 		__raw_writel(r, base + USB_DWC_CTRL1);
192 		r = __raw_readl(base + USB_DWC_CTRL3);
194 		__raw_writel(r, base + USB_DWC_CTRL3);
197 		__au1300_usb_phyctl(base, enable);
201 static inline void __au1300_udc_control(void __iomem *base, int enable)
206 		r = __raw_readl(base + USB_DWC_CTRL1);
208 		__raw_writel(r, base + USB_DWC_CTRL1);
211 		__au1300_usb_phyctl(base, enable);
213 		r = __raw_readl(base + USB_INT_ENABLE);
215 		__raw_writel(r, base + USB_INT_ENABLE);
218 		r = __raw_readl(base + USB_INT_ENABLE);
220 		__raw_writel(r, base + USB_INT_ENABLE);
223 		r = __raw_readl(base + USB_DWC_CTRL1);
225 		__raw_writel(r, base + USB_DWC_CTRL1);
228 		__au1300_usb_phyctl(base, enable);
232 static inline void __au1300_otg_control(void __iomem *base, int enable)
236 		r = __raw_readl(base + USB_DWC_CTRL3);
238 		__raw_writel(r, base + USB_DWC_CTRL3);
241 		r = __raw_readl(base + USB_DWC_CTRL1);
243 		__raw_writel(r, base + USB_DWC_CTRL1);
246 		__au1300_usb_phyctl(base, enable);
248 		r = __raw_readl(base + USB_DWC_CTRL1);
250 		__raw_writel(r, base + USB_DWC_CTRL1);
253 		r = __raw_readl(base + USB_DWC_CTRL3);
255 		__raw_writel(r, base + USB_DWC_CTRL3);
258 		__au1300_usb_phyctl(base, enable);
264 	void __iomem *base =
270 		__au1300_ohci_control(base, enable, 0);
273 		__au1300_ohci_control(base, enable, 1);
276 		__au1300_ehci_control(base, enable);
279 		__au1300_udc_control(base, enable);
282 		__au1300_otg_control(base, enable);
292 	void __iomem *base =
300 	__raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
302 	__raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
304 	__raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
306 	__raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
309 	__raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
313 static inline void __au1200_ohci_control(void __iomem *base, int enable)
315 	unsigned long r = __raw_readl(base + AU1200_USBCFG);
317 		__raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
321 		__raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
327 static inline void __au1200_ehci_control(void __iomem *base, int enable)
329 	unsigned long r = __raw_readl(base + AU1200_USBCFG);
331 		__raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
337 		__raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
343 static inline void __au1200_udc_control(void __iomem *base, int enable)
345 	unsigned long r = __raw_readl(base + AU1200_USBCFG);
347 		__raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
352 		__raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
373 	void __iomem *base =
382 		__au1200_ohci_control(base, enable);
385 		__au1200_udc_control(base, enable);
391 		__au1200_ehci_control(base, enable);
404 	void __iomem *base =
406 	__raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
413 	void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
414 	unsigned long r = __raw_readl(base);
421 	__raw_writel(r, base);
429 	void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
430 	unsigned long r = __raw_readl(base + creg);
433 		__raw_writel(r | USBHEN_CE, base + creg);
436 		__raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
441 		while (__raw_readl(base + creg),
442 			!(__raw_readl(base + creg) & USBHEN_RD))
445 		__raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
506 	void __iomem *base = (void __iomem *)KSEG1ADDR(br);
509 		alchemy_usb_pmdata[0] = __raw_readl(base + creg);
511 		__raw_writel(0, base + 0x04);
513 		__raw_writel(0, base + creg);
516 		__raw_writel(alchemy_usb_pmdata[0], base + creg);
523 	void __iomem *base =
528 		alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
529 		alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
535 		__raw_writel(alchemy_usb_pmdata[0], base + 0x00);
536 		__raw_writel(alchemy_usb_pmdata[1], base + 0x04);
543 	void __iomem *base =
547 		alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
550 		__raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);