Lines Matching refs:ohci
13 * Modified for LH7A404 from ohci-sa1111.c
16 * Modified for pxa27x from ohci-lh7a404.c
27 #include <mach/ohci.h>
104 struct ohci_hcd ohci;
123 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
125 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
126 uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
150 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
151 __raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
159 static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
162 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
163 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
195 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
196 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
199 static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
201 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
203 __raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
205 __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
214 static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
222 clk_prepare_enable(ohci->clk);
224 pxa27x_reset_hc(ohci);
226 uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
227 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
229 while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
232 pxa27x_setup_hc(ohci, inf);
241 pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);
243 uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
244 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
245 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
252 static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
260 pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
265 pxa27x_reset_hc(ohci);
268 uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
269 __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
272 clk_disable_unprepare(ohci->clk);
296 struct pxa27x_ohci *ohci;
345 ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
346 ohci->dev = &pdev->dev;
347 ohci->clk = usb_clk;
348 ohci->mmio_base = (void __iomem *)hcd->regs;
350 if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
356 pxa27x_ohci_select_pmm(ohci, inf->port_mode);
367 pxa27x_stop_hc(ohci, &pdev->dev);
395 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
398 pxa27x_stop_hc(ohci, &pdev->dev);
402 clk_put(ohci->clk);
410 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
413 ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
416 ohci->num_ports = 3;
418 if ((ret = ohci_init(ohci)) < 0)
421 if ((ret = ohci_run (ohci)) < 0) {
499 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
501 if (time_before(jiffies, ohci->ohci.next_statechange))
503 ohci->ohci.next_statechange = jiffies;
505 pxa27x_stop_hc(ohci, dev);
512 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
516 if (time_before(jiffies, ohci->ohci.next_statechange))
518 ohci->ohci.next_statechange = jiffies;
520 if ((status = pxa27x_start_hc(ohci, dev)) < 0)
524 pxa27x_ohci_select_pmm(ohci, inf->port_mode);
537 MODULE_ALIAS("platform:pxa27x-ohci");
544 .name = "pxa27x-ohci",