Searched defs:BIT_5 (Results 1 - 4 of 4) sorted by relevance

/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h199 #define BIT_5 0x20 macro
/drivers/scsi/
H A Dqla1280.h31 #define BIT_5 0x20 macro
134 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */
137 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */
138 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */
319 #define TP_PPR BIT_5 /* PPR */
/drivers/scsi/qla4xxx/
H A Dql4_def.h76 #define BIT_5 0x20 macro
/drivers/scsi/qla2xxx/
H A Dqla_def.h64 #define BIT_5 0x20 macro
219 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
410 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
605 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
626 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
758 #define MBX_5 BIT_5
1272 #define CF_READ BIT_5
1366 #define PO_DISABLE_INCR_REF_TAG BIT_5
1445 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2547 #define DT_ISP6312 BIT_5
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