Searched defs:hz (Results 1 - 25 of 25) sorted by relevance

/drivers/clocksource/
H A Dmmio.c47 * @hz: Frequency of the clocksource in Hz
53 unsigned long hz, int rating, unsigned bits,
72 return clocksource_register_hz(&cs->clksrc, hz);
52 clocksource_mmio_init(void __iomem *base, const char *name, unsigned long hz, int rating, unsigned bits, cycle_t (*read)(struct clocksource *)) argument
/drivers/spi/
H A Dspi-bitbang.c146 u32 hz; local
150 hz = t->speed_hz;
153 hz = 0;
169 if (!hz)
170 hz = spi->max_speed_hz;
171 if (hz) {
172 cs->nsecs = (1000000000/2) / hz;
H A Dspi-bcm63xx.c124 u32 hz; local
128 hz = (t) ? t->speed_hz : spi->max_speed_hz;
132 if (hz <= bcm63xx_spi_freq_table[i][0]) {
148 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
149 clk_cfg, hz);
H A Dspi-oc-tiny.c66 static unsigned int tiny_spi_baud(struct spi_device *spi, unsigned int hz) argument
70 return min(DIV_ROUND_UP(hw->freq, hz * 2), (1U << hw->baudwidth)) - 1;
H A Dspi-au1550.c239 unsigned bpw, hz; local
243 hz = spi->max_speed_hz;
248 hz = t->speed_hz;
256 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
258 hz);
278 cfg |= au1550_spi_baudcfg(hw, hz);
H A Dspi-omap-uwire.c325 unsigned hz; local
375 hz = spi->max_speed_hz;
377 hz = t->speed_hz;
379 if (!hz) {
402 div2 = (rate / div1 + hz - 1) / hz;
408 dev_name(&spi->dev), rate / 10 / 8, hz);
H A Dspi-s3c24xx.c39 * @hz: Last frequency calculated for @sppre field.
45 unsigned int hz; member in struct:s3c24xx_spi_devstate
130 unsigned int hz; local
135 hz = t ? t->speed_hz : spi->max_speed_hz;
140 if (!hz)
141 hz = spi->max_speed_hz;
161 if (cs->hz != hz) {
163 div = DIV_ROUND_UP(clk, hz * 2) - 1;
169 div, hz, cl
[all...]
H A Dspi-stmp.c129 u32 hz; local
143 hz = 1000 * ss->speed_khz / ss->divider;
145 hz = min(hz, spi->max_speed_hz);
147 hz = min(hz, t->speed_hz);
149 if (hz == 0) {
161 hz, ss->speed_khz, ss->divider,
164 if (ss->speed_khz * 1000 / ss->divider < hz) {
166 __func__, hz);
[all...]
H A Dspi-fsl-espi.c136 u32 hz = 0; local
141 hz = t->speed_hz;
152 if (!hz)
153 hz = spi->max_speed_hz;
181 if ((mpc8xxx_spi->spibrg / hz) > 64) {
183 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
187 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
191 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
H A Dspi-davinci.c284 u32 hz = 0, spifmt = 0, prescale = 0; local
293 hz = t->speed_hz;
315 if (!hz)
316 hz = spi->max_speed_hz;
320 prescale = davinci_spi_get_prescale(dspi, hz);
H A Dspi-fsl-spi.c233 u32 hz = 0; local
240 hz = t->speed_hz;
252 if (!hz)
253 hz = spi->max_speed_hz;
277 if ((mpc8xxx_spi->spibrg / hz) > 64) {
279 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
283 hz, mpc8xxx_spi->spibrg / 1024);
287 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
H A Dspi-sh-msiof.c374 unsigned long hz; local
376 hz = t ? t->speed_hz : 0;
377 if (!hz)
378 hz = spi->max_speed_hz;
379 return hz;
387 /* noting to check hz values against since parent clock is disabled */
H A Dspi-sirf.c378 int hz = 0; local
387 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
392 regval = (sspi->ctrl_freq / (2 * hz)) - 1;
395 dev_err(&spi->dev, "Speed %d not supported\n", hz);
/drivers/ssb/
H A Ddriver_mipscore.c238 unsigned long hz, ns; local
247 hz = ssb_clockspeed(bus);
248 if (!hz)
249 hz = 100000000;
250 ns = 1000000000 / hz;
/drivers/staging/sm7xx/
H A Dsmtcfb.h114 int hz; member in struct:ModeInit
H A Dsmtcfb.c91 u_int hz; member in struct:par_info
164 "sfb->fb.var.bits_per_pixel = %d ppar_info->hz = %d\n",
166 sfb->fb.var.bits_per_pixel, ppar_info->hz);
172 VGAMode[j].hz == ppar_info->hz) {
176 "VGAMode[j].hz=%d\n",
178 VGAMode[j].bpp, VGAMode[j].hz);
665 hw.hz = 60;
/drivers/mmc/host/
H A Dcb710-mmc.c28 static void cb710_mmc_select_clock_divider(struct mmc_host *mmc, int hz) argument
46 if (hz >= src_hz >> cb710_clock_divider_log2[divider_idx])
60 hz, src_freq_idx, divider_idx & 7, divider_idx & 8); local
/drivers/gpu/drm/via/
H A Dvia_verifier.c114 hazard_t hz; member in struct:__anon671
347 investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) argument
351 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
357 switch (hz) {
629 hazard_t hz; local
696 if ((hz = hz_table[cmd >> 24])) {
697 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
1100 table[init_table[i].code] = init_table[i].hz;
/drivers/input/keyboard/
H A Dlm8323.c456 int div512, perstep, steps, hz, up, kill; local
481 hz = 32768 / 512;
484 hz = 32768 / 16;
487 perstep = (hz * pwm->fade_time) / (steps * 1000);
/drivers/media/video/
H A Dsaa7115.c259 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
308 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
362 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
381 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
390 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
419 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
440 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
700 u32 hz; local
714 /* hz is the refresh rate times 100 */
715 hz
[all...]
/drivers/video/
H A Dfbmon.c705 int num_modes, hz, hscan, pixclock; local
731 hz = (hscan + vtotal / 2) / vtotal;
745 if (specs->vfmax == 0 || specs->vfmax < hz)
746 specs->vfmax = hz;
748 if (specs->vfmin == 0 || specs->vfmin > hz)
749 specs->vfmin = hz;
/drivers/mmc/core/
H A Dcore.c738 * is below "hz".
740 static void __mmc_set_clock(struct mmc_host *host, unsigned int hz) argument
742 WARN_ON(hz < host->f_min);
744 if (hz > host->f_max)
745 hz = host->f_max;
747 host->ios.clock = hz;
751 void mmc_set_clock(struct mmc_host *host, unsigned int hz) argument
754 __mmc_set_clock(host, hz);
/drivers/tty/vt/
H A Dkeyboard.c237 unsigned int *hz = data; local
242 input_inject_event(handle, EV_SND, SND_TONE, *hz);
243 if (*hz)
247 input_inject_event(handle, EV_SND, SND_BELL, *hz ? 1 : 0);
262 void kd_mksound(unsigned int hz, unsigned int ticks) argument
266 input_handler_for_each_handle(&kbd_handler, &hz, kd_sound_helper);
268 if (hz && ticks)
/drivers/video/aty/
H A Dradeon_base.c462 unsigned long long hz, vclk; local
502 hz = 1000000/total_usecs;
506 vclk = (long long)hTotal * (long long)vTotal * hz;
/drivers/net/wan/
H A Ddscc4.c877 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz) argument
881 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
884 dpriv->pci_priv->xtal_hz = hz;

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