Searched defs:tile (Results 1 - 13 of 13) sorted by relevance

/drivers/gpu/drm/nouveau/
H A Dnv40_fb.c10 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
14 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
15 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
16 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
20 nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit);
21 nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch);
22 nv_wr32(dev, NV40_PFB_TILE(i), tile->addr);
H A Dnv10_fb.c11 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
13 tile->addr = 0x80000000 | addr;
14 tile->limit = max(1u, addr + size) - 1;
15 tile->pitch = pitch;
22 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
24 tile->addr = tile->limit = tile
31 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
[all...]
H A Dnv20_fb.c18 spin_lock(&dev_priv->tile.lock);
22 spin_unlock(&dev_priv->tile.lock);
33 spin_lock(&dev_priv->tile.lock);
35 spin_unlock(&dev_priv->tile.lock);
45 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
48 tile->addr = 0x00000001 | addr;
49 tile->limit = max(1u, addr + size) - 1;
50 tile->pitch = pitch;
54 * if a given tile i
81 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
91 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
[all...]
H A Dnv30_fb.c37 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
39 tile->addr = addr | 1;
40 tile->limit = max(1u, addr + size) - 1;
41 tile->pitch = pitch;
48 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
50 tile->addr = tile->limit = tile
[all...]
H A Dnv20_graph.c477 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
479 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
480 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
481 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
484 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->limit);
486 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->pitch);
488 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->addr);
491 nv_wr32(dev, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
493 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile
[all...]
H A Dnv31_mpeg.c237 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
239 nv_wr32(dev, 0x00b008 + (i * 0x10), tile->pitch);
240 nv_wr32(dev, 0x00b004 + (i * 0x10), tile->limit);
241 nv_wr32(dev, 0x00b000 + (i * 0x10), tile->addr);
H A Dnv40_graph.c133 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
142 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
143 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
144 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
145 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
146 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
147 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
151 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
152 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile
[all...]
H A Dnv10_graph.c900 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
902 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), tile->limit);
903 nv_wr32(dev, NV10_PGRAPH_TSIZE(i), tile->pitch);
904 nv_wr32(dev, NV10_PGRAPH_TILE(i), tile->addr);
H A Dnouveau_mem.c49 struct nouveau_tile_reg *tile, uint32_t addr,
55 int i = tile - dev_priv->tile.reg, j;
58 nouveau_fence_unref(&tile->fence);
60 if (tile->pitch)
87 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; local
89 spin_lock(&dev_priv->tile.lock);
91 if (!tile->used &&
92 (!tile
48 nv10_mem_update_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile, uint32_t addr, uint32_t size, uint32_t pitch, uint32_t flags) argument
102 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile, struct nouveau_fence *fence) argument
126 struct nouveau_tile_reg *tile, *found = NULL; local
[all...]
H A Dnouveau_drv.h121 struct nouveau_tile_reg *tile; member in struct:nouveau_bo
797 } tile; member in struct:drm_nouveau_private
947 struct nouveau_tile_reg *tile,
/drivers/video/
H A Dgbefb.c710 | 128 [tile 0] [tile 1]
713 4 128 [tile 2] [tile 3]
716 128 [tile 4] [tile 5]
719 v 96 [tile 6] [tile 7]
725 DMA hardware is fooled into thinking the screen is only one tile
730 framebuffer as a continuous virtual memory. The GBE tile tabl
1014 u16 *tile; local
[all...]
H A Dcirrusfb.c890 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); local
900 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
/drivers/hid/
H A Dhid-picolcd.c86 * each. Each tile has 8x64 pixel, each data byte representing
87 * a 1-bit wide vertical line of the tile.
89 * The display can be updated at a tile granularity.
314 /* Send a given tile to PicoLCD */
315 static int picolcd_fb_send_tile(struct hid_device *hdev, int chip, int tile) argument
332 hid_set_field(report1->field[0], 4, 0xb8 | tile);
345 tdata = data->fb_vbitmap + (tile * 4 + chip) * 64;
358 /* Translate a single tile*/
360 int chip, int tile)
364 u8 *vdata = vbitmap + (tile *
359 picolcd_fb_update_tile(u8 *vbitmap, const u8 *bitmap, int bpp, int chip, int tile) argument
440 int chip, tile, n; local
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