1#include "drmP.h" 2#include "drm.h" 3#include "nouveau_drv.h" 4#include "nouveau_drm.h" 5 6void 7nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr, 8 uint32_t size, uint32_t pitch, uint32_t flags) 9{ 10 struct drm_nouveau_private *dev_priv = dev->dev_private; 11 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 12 13 tile->addr = 0x80000000 | addr; 14 tile->limit = max(1u, addr + size) - 1; 15 tile->pitch = pitch; 16} 17 18void 19nv10_fb_free_tile_region(struct drm_device *dev, int i) 20{ 21 struct drm_nouveau_private *dev_priv = dev->dev_private; 22 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 23 24 tile->addr = tile->limit = tile->pitch = tile->zcomp = 0; 25} 26 27void 28nv10_fb_set_tile_region(struct drm_device *dev, int i) 29{ 30 struct drm_nouveau_private *dev_priv = dev->dev_private; 31 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 32 33 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); 34 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); 35 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); 36} 37 38int 39nv1a_fb_vram_init(struct drm_device *dev) 40{ 41 struct drm_nouveau_private *dev_priv = dev->dev_private; 42 struct pci_dev *bridge; 43 uint32_t mem, mib; 44 45 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); 46 if (!bridge) { 47 NV_ERROR(dev, "no bridge device\n"); 48 return 0; 49 } 50 51 if (dev_priv->chipset == 0x1a) { 52 pci_read_config_dword(bridge, 0x7c, &mem); 53 mib = ((mem >> 6) & 31) + 1; 54 } else { 55 pci_read_config_dword(bridge, 0x84, &mem); 56 mib = ((mem >> 4) & 127) + 1; 57 } 58 59 dev_priv->vram_size = mib * 1024 * 1024; 60 return 0; 61} 62 63int 64nv10_fb_vram_init(struct drm_device *dev) 65{ 66 struct drm_nouveau_private *dev_priv = dev->dev_private; 67 u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA); 68 u32 cfg0 = nv_rd32(dev, 0x100200); 69 70 dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; 71 72 if (cfg0 & 0x00000001) 73 dev_priv->vram_type = NV_MEM_TYPE_DDR1; 74 else 75 dev_priv->vram_type = NV_MEM_TYPE_SDRAM; 76 77 return 0; 78} 79 80int 81nv10_fb_init(struct drm_device *dev) 82{ 83 struct drm_nouveau_private *dev_priv = dev->dev_private; 84 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 85 int i; 86 87 /* Turn all the tiling regions off. */ 88 pfb->num_tiles = NV10_PFB_TILE__SIZE; 89 for (i = 0; i < pfb->num_tiles; i++) 90 pfb->set_tile_region(dev, i); 91 92 return 0; 93} 94 95void 96nv10_fb_takedown(struct drm_device *dev) 97{ 98 struct drm_nouveau_private *dev_priv = dev->dev_private; 99 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 100 int i; 101 102 for (i = 0; i < pfb->num_tiles; i++) 103 pfb->free_tile_region(dev, i); 104} 105