Searched refs:base (Results 201 - 225 of 1118) sorted by relevance

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/drivers/gpu/drm/nouveau/
H A Dnv84_crypt.c32 struct nouveau_exec_engine base; member in struct:nv84_crypt_engine
180 pcrypt->base.destroy = nv84_crypt_destroy;
181 pcrypt->base.init = nv84_crypt_init;
182 pcrypt->base.fini = nv84_crypt_fini;
183 pcrypt->base.context_new = nv84_crypt_context_new;
184 pcrypt->base.context_del = nv84_crypt_context_del;
185 pcrypt->base.object_new = nv84_crypt_object_new;
186 pcrypt->base.tlb_flush = nv84_crypt_tlb_flush;
190 NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base);
H A Dnva3_copy.c34 struct nouveau_exec_engine base; member in struct:nva3_copy_engine
213 pcopy->base.destroy = nva3_copy_destroy;
214 pcopy->base.init = nva3_copy_init;
215 pcopy->base.fini = nva3_copy_fini;
216 pcopy->base.context_new = nva3_copy_context_new;
217 pcopy->base.context_del = nva3_copy_context_del;
218 pcopy->base.object_new = nva3_copy_object_new;
219 pcopy->base.tlb_flush = nva3_copy_tlb_flush;
223 NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
/drivers/gpu/drm/udl/
H A Dudl_drv.h66 struct drm_gem_object base; member in struct:udl_gem_object
71 #define to_udl_bo(x) container_of(x, struct udl_gem_object, base)
74 struct drm_framebuffer base; member in struct:udl_framebuffer
79 #define to_udl_fb(x) container_of(x, struct udl_framebuffer, base)
/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_fence.c52 struct ttm_base_object base; member in struct:vmw_user_fence
550 struct ttm_base_object *base = *p_base; local
552 container_of(base, struct vmw_user_fence, base);
596 * The base object holds a reference which is freed in
600 ret = ttm_base_object_init(tfile, &ufence->base, false,
607 * Free the base object's reference
614 *p_handle = ufence->base.hash.key;
688 struct ttm_base_object *base; local
707 base
746 struct ttm_base_object *base; local
992 struct drm_pending_event base; member in struct:vmw_event_fence_pending
1082 struct ttm_base_object *base = local
[all...]
/drivers/mtd/maps/
H A Dpismo.c39 phys_addr_t base; member in struct:pismo_mem
96 phys_addr_t base = region->base; local
99 if (base == ~0)
102 res.start = base;
103 res.end = base + region->size - 1;
158 const struct pismo_cs_block *cs, phys_addr_t base)
163 region.base = base;
177 * The memory controller can also tell us the base addres
157 pismo_add_one(struct pismo_data *pismo, int i, const struct pismo_cs_block *cs, phys_addr_t base) argument
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/drivers/mtd/onenand/
H A Dgeneric.c55 info->onenand.base = ioremap(res->start, size);
56 if (!info->onenand.base) {
82 iounmap(info->onenand.base);
102 iounmap(info->onenand.base);
/drivers/net/ethernet/amd/
H A Dhplance.c156 lp->lance.base = va;
177 out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
178 } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
185 out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
186 } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
194 value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
195 } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
208 out_8(lp->base + HPLANCE_STATUS, LE_IE);
217 out_8(lp->base + HPLANCE_STATUS, 0); /* disable interrupts at boardlevel */
/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h48 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
49 (iowrite16_rep(base + offset, data, count))
51 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
52 (ioread16_rep(base + (offset << 1), data, count))
/drivers/net/wireless/rtlwifi/
H A DMakefile3 base.o \
/drivers/pcmcia/
H A Dbcm63xx_pcmcia.h33 /* base remapped address of registers */
34 void __iomem *base; member in struct:bcm63xx_pcmcia_socket
56 /* base address of io memory */
/drivers/scsi/
H A Dsim710.c107 printk(KERN_NOTICE "sim710: irq = %d, clock = %d, base = 0x%lx, scsi_id = %d\n",
122 hostdata->base = ioport_map(base_addr, 64);
135 host->base = base_addr;
168 release_region(host->base, 64);
194 unsigned int base; local
209 * 01BB & 01BA port base by bits 7,6,5,4,3,2 in pos[2]
223 * 00F4 port base by bits 3,2,1 in pos[0]
241 base = io_01bb_by_pos[(pos[2] & 0xFC) >> 2];
251 base = io_004f_by_pos[((pos[0] & 0x0E) >> 1)];
261 base
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/drivers/staging/telephony/
H A Dphonedev.c90 int base; local
94 base = 0;
98 base = unit;
103 for (i = base; i < end; i++) {
/drivers/staging/tidspbridge/include/dspbridge/
H A Drmm.h38 u32 base; /* Base of the segment */ member in struct:rmm_segment
/drivers/staging/usbip/
H A Dvhci_tx.c34 pdup->base.command = USBIP_CMD_SUBMIT;
35 pdup->base.seqnum = priv->seqnum;
36 pdup->base.devid = vdev->devid;
37 pdup->base.direction = usb_pipein(urb->pipe) ?
39 pdup->base.ep = usb_pipeendpoint(urb->pipe);
177 pdu_header.base.command = USBIP_CMD_UNLINK;
178 pdu_header.base.seqnum = unlink->seqnum;
179 pdu_header.base.devid = vdev->devid;
180 pdu_header.base.ep = 0;
/drivers/usb/host/whci/
H A Dinit.c32 le_writel(WUSBCMD_WHCRESET, whc->base + WUSBCMD);
33 whci_wait_for(&whc->umc->dev, whc->base + WUSBCMD, WUSBCMD_WHCRESET, 0,
45 le_writeq(whc->di_buf_dma, whc->base + WUSBDEVICEINFOADDR);
54 le_writeq(whc->dn_buf_dma, whc->base + WUSBDNTSBUFADDR);
93 whc->base = ioremap(start, len);
94 if (!whc->base) {
103 whcsparams = le_readl(whc->base + WHCSPARAMS);
182 if (whc->base)
183 iounmap(whc->base);
/drivers/spi/
H A Dspi-omap-100k.c97 /* Virtual base address of the controller */
98 void __iomem *base; member in struct:omap1_spi100k
105 void __iomem *base; member in struct:omap1_spi100k_cs
124 val = readw(spi100k->base + SPI_SETUP1);
126 writew(val, spi100k->base + SPI_SETUP1);
135 val = readw(spi100k->base + SPI_SETUP1);
137 writew(val, spi100k->base + SPI_SETUP1);
151 writew( data , spi100k->base + SPI_TX_MSB);
156 spi100k->base + SPI_CTRL);
159 while((readw(spi100k->base
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H A Dspi-imx.c86 void __iomem *base; member in struct:spi_imx_data
120 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
140 writel(val, spi_imx->base + MXC_CSPITXDATA); \
226 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
249 writel(val, spi_imx->base + MX51_ECSPI_INT);
256 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
258 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
294 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
295 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
302 return readl(spi_imx->base
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/drivers/isdn/hardware/mISDN/
H A Dnetjet.c83 u32 base; member in struct:tiger_hw
138 outb(0, card->base + NJ_IRQMASK0);
139 outb(0, card->base + NJ_IRQMASK1);
151 outb(card->auxd, card->base + NJ_AUXDATA);
152 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
163 outb(card->auxd, card->base + NJ_AUXDATA);
164 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
173 outb(card->auxd, card->base + NJ_AUXDATA);
174 insb(card->base + NJ_ISAC_OFF, data, size);
183 outb(card->auxd, card->base
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/drivers/input/keyboard/
H A Dsamsung-keypad.c72 void __iomem *base; member in struct:samsung_keypad
104 writel(val, keypad->base + SAMSUNG_KEYIFCOL);
107 val = readl(keypad->base + SAMSUNG_KEYIFROW);
112 writel(0, keypad->base + SAMSUNG_KEYIFCOL);
165 val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
167 writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
195 val = readl(keypad->base + SAMSUNG_KEYIFCON);
197 writel(val, keypad->base + SAMSUNG_KEYIFCON);
200 writel(0, keypad->base + SAMSUNG_KEYIFCOL);
217 writel(~0x0, keypad->base
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/drivers/net/ethernet/faraday/
H A Dftgmac100.c57 void __iomem *base; member in struct:ftgmac100
96 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
103 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
109 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
114 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
123 iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
127 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
143 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
144 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
149 /* setup ring buffer base register
[all...]
/drivers/video/
H A Dmxsfb.c162 void __iomem *base; /* registers */ member in struct:mxsfb_info
335 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
338 reg = readl(host->base + LCDC_VDCTRL4);
340 writel(reg, host->base + LCDC_VDCTRL4);
342 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
359 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
363 reg = readl(host->base + LCDC_CTRL);
369 writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR);
402 writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
411 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base
[all...]
/drivers/isdn/hisax/
H A Dbkm_a4t.c134 pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base);
170 if (cs->hw.ax.base) {
171 iounmap((void *) cs->hw.ax.base);
172 cs->hw.ax.base = 0;
180 I20_REGISTER_FILE *pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base);
193 I20_REGISTER_FILE *pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base);
288 cs->hw.ax.base = (long) ioremap(pci_memaddr, 4096);
290 pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base);
294 cs->hw.ax.base, cs->hw.ax.base
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/drivers/ide/
H A Dqd65xx.c50 * base: Timer1
53 * base+0x01: Config (R/O)
65 * base+0x02: Timer2 (qd6580 only)
68 * base+0x03: Control (qd6580 only)
218 u8 base = (hwif->config_data & 0xff00) >> 8; local
292 u8 base = (hwif->config_data & 0xff00) >> 8; local
302 u8 base = (hwif->config_data & 0xff00) >> 8; local
354 static int __init qd_probe(int base) argument
362 if (! ((config & QD_CONFIG_BASEPORT) >> 1 == (base == 0xb0)) )
372 if (qd_testreg(base))
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/drivers/media/video/
H A Dsh_mobile_csi2.c41 void __iomem *base; member in struct:sh_csi2
126 iowrite32(tmp, priv->base + SH_CSI2_VCDT);
167 iowrite32(0x00000001, priv->base + SH_CSI2_TREF);
169 iowrite32(0x00000001, priv->base + SH_CSI2_SRST);
171 iowrite32(0x00000000, priv->base + SH_CSI2_SRST);
192 iowrite32(tmp, priv->base + SH_CSI2_PHYCNT);
199 iowrite32(tmp, priv->base + SH_CSI2_CHKSUM);
333 priv->base = ioremap(res->start, resource_size(res));
334 if (!priv->base) {
360 iounmap(priv->base);
[all...]
/drivers/net/can/cc770/
H A Dcc770_isa.c145 unsigned long base = (unsigned long)priv->reg_base; local
150 outb(reg, base);
151 val = inb(base + 1);
160 unsigned long base = (unsigned long)priv->reg_base; local
164 outb(reg, base);
165 outb(val, base + 1);
173 void __iomem *base = NULL; local
186 base = ioremap_nocache(mem[idx], iosize);
187 if (!base) {
211 priv->reg_base = base;
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