Searched refs:base (Results 76 - 100 of 1118) sorted by relevance

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/drivers/gpio/
H A Dgpio-pl061.c58 void __iomem *base; member in struct:pl061_gpio
78 gpiodir = readb(chip->base + GPIODIR);
80 writeb(gpiodir, chip->base + GPIODIR);
97 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
98 gpiodir = readb(chip->base + GPIODIR);
100 writeb(gpiodir, chip->base + GPIODIR);
106 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
116 return !!readb(chip->base + (1 << (offset + 2)));
123 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
149 gpioiev = readb(chip->base
[all...]
/drivers/i2c/busses/
H A Di2c-sirf.c69 void __iomem *base; member in struct:sirfsoc_i2c
94 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
114 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
127 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
129 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
135 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
141 u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
146 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
163 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
179 writel(regval, siic->base
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H A Di2c-imx.c122 void __iomem *base; member in struct:imx_i2c_struct
147 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
178 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
195 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
197 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
198 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
204 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
206 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
213 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
224 temp = readb(i2c_imx->base
473 void __iomem *base; local
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H A Di2c-intel-mid.c61 * @base: register base
78 void __iomem *base; member in struct:intel_mid_i2c_private
328 writel(0, i2c->base + IC_ENABLE);
332 while ((ret1 = readl(i2c->base + IC_ENABLE_STATUS) & 0x1)
333 || (ret2 = readl(i2c->base + IC_STATUS) & 0x1)) {
335 writel(0, i2c->base + IC_ENABLE);
345 readl(i2c->base + IC_CLR_INTR);
346 readl(i2c->base + IC_CLR_STOP_DET);
347 readl(i2c->base
956 void __iomem *base = NULL; local
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/drivers/rtc/
H A Drtc-pl031.c73 void __iomem *base; member in struct:pl031_local
85 writel(RTC_BIT_AI, ldata->base + RTC_ICR);
87 imsc = readl(ldata->base + RTC_IMSC);
90 writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
92 writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
157 pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
158 readl(ldata->base + RTC_YDR), tm);
172 writel(bcd_year, ldata->base + RTC_YLR);
173 writel(time, ldata->base + RTC_LR);
184 ret = pl031_stv2_time_to_tm(readl(ldata->base
[all...]
H A Drtc-s3c.c178 void __iomem *base = s3c_rtc_base; local
182 rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
183 rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
184 rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
185 rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
186 rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
187 rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
220 void __iomem *base = s3c_rtc_base; local
235 writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
236 writeb(bin2bcd(tm->tm_min), base
249 void __iomem *base = s3c_rtc_base; local
311 void __iomem *base = s3c_rtc_base; local
377 void __iomem *base = s3c_rtc_base; local
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/drivers/clocksource/
H A Dcyclone.c12 #define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */
37 unsigned long base; /* saved value from CBAR */ local
49 /* find base address: */
57 base = readl(reg);
59 if (!base) {
65 offset = base + CYCLONE_PMCC_OFFSET;
75 offset = base + CYCLONE_MPCS_OFFSET;
85 offset = base + CYCLONE_MPMC_OFFSET;
/drivers/spi/
H A Dspi-altera.c53 void __iomem *base; member in struct:altera_spi
78 hw->base + ALTERA_SPI_SLAVE_SEL);
80 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
85 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
86 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL);
93 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
98 hw->base + ALTERA_SPI_SLAVE_SEL);
100 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
143 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
146 writel(hw_txbyte(hw, 0), hw->base
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/drivers/dma/
H A Dcoh901318.c81 struct coh901318_base *base; member in struct:coh901318_chan
196 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
202 return &cohc->base->platform->chan_conf[cohc->id].param;
208 return &cohc->base->platform->chan_conf[cohc->id];
214 struct powersave *pm = &cohc->base->pm;
222 cohc->base->platform->access_memory_state(cohc->base->dev,
231 struct powersave *pm = &cohc->base->pm;
237 cohc->base->platform->access_memory_state(cohc->base
785 struct coh901318_base *base = dev_id; local
1393 coh901318_base_init(struct dma_device *dma, const int *pick_chans, struct coh901318_base *base) argument
1435 struct coh901318_base *base; local
1568 struct coh901318_base *base = platform_get_drvdata(pdev); local
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/drivers/scsi/
H A Daha1542.h38 #define STATUS(base) base
48 #define INTRFLAGS(base) (STATUS(base)+2)
57 #define CONTROL(base) STATUS(base)
64 #define DATA(base) (STATUS(base)+1)
H A Dsni_53c710.c70 unsigned long base; local
79 base = res->start;
88 hostdata->base = ioremap_nocache(base, 0x100);
100 host->base = base;
115 iounmap(hostdata->base);
129 iounmap(hostdata->base);
/drivers/isdn/hisax/
H A Dnj_s.c36 s1val = bytein(cs->hw.njet.base + NETJET_IRQSTAT1);
55 s0val = bytein(cs->hw.njet.base + NETJET_IRQSTAT0);
61 byteout(cs->hw.njet.base + NETJET_IRQSTAT0, s0val);
64 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) <
65 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ))
70 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) <
71 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ))
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
116 byteout(cs->hw.njet.base
[all...]
H A Denternow_pci.c85 * From address hw.njet.base + TJ_AMD_PORT onwards, the AMD
87 * -> 0x01 of the AMD at hw.njet.base + 0C4 */
129 outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1);
131 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL);
166 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL);
167 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1);
202 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA);
207 outb(0x00, cs->hw.njet.base
[all...]
H A Dnj_u.c36 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) &
49 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) <
50 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ))
55 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) <
56 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ))
87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
96 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ);
97 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ);
142 cs->hw.njet.base
[all...]
/drivers/net/wireless/brcm80211/brcmfmac/
H A Dsdio_chip.c35 /* chip core base & ramsize */
97 CORE_SB(ci->c_inf[idx].base, sbidhigh), 4);
122 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
160 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
165 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
172 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
174 CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
178 CORE_SB(ci->c_inf[idx].base, sbtmstatelow), 4);
181 CORE_SB(ci->c_inf[idx].base, sbtmstatehigh), 4) &
185 CORE_SB(ci->c_inf[idx].base, sbtmstatehig
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/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_scrn.c32 container_of(x, struct vmw_screen_object_unit, base.crtc)
34 container_of(x, struct vmw_screen_object_unit, base.encoder)
36 container_of(x, struct vmw_screen_object_unit, base.connector)
48 struct vmw_display_unit base; member in struct:vmw_screen_object_unit
59 vmw_display_unit_cleanup(&sou->base);
93 if (!sou->active_implicit && sou->base.is_implicit) {
130 cmd->obj.id = sou->base.unit;
132 (sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0);
135 if (sou->base.is_implicit) {
139 cmd->obj.root.x = sou->base
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/drivers/input/serio/
H A Daltera_ps2.c29 void __iomem *base; member in struct:ps2if
43 while ((status = readl(ps2if->base)) & 0xffff0000) {
58 writel(val, ps2if->base);
67 while (readl(ps2if->base) & 0xffff0000)
70 writel(1, ps2if->base + 4); /* enable rx irq */
78 writel(0, ps2if->base); /* disable rx irq */
127 ps2if->base = ioremap(ps2if->iomem_res->start,
129 if (!ps2if->base) {
141 dev_info(&pdev->dev, "base %p, irq %d\n", ps2if->base, ps2i
[all...]
/drivers/virtio/
H A Dvirtio_mmio.c73 void __iomem *base; member in struct:virtio_mmio_device
107 writel(0, vm_dev->base + VIRTIO_MMIO_HOST_FEATURES_SEL);
109 return readl(vm_dev->base + VIRTIO_MMIO_HOST_FEATURES);
121 writel(i, vm_dev->base + VIRTIO_MMIO_GUEST_FEATURES_SEL);
123 vm_dev->base + VIRTIO_MMIO_GUEST_FEATURES);
135 ptr[i] = readb(vm_dev->base + VIRTIO_MMIO_CONFIG + offset + i);
146 writeb(ptr[i], vm_dev->base + VIRTIO_MMIO_CONFIG + offset + i);
153 return readl(vm_dev->base + VIRTIO_MMIO_STATUS) & 0xff;
163 writel(status, vm_dev->base + VIRTIO_MMIO_STATUS);
171 writel(0, vm_dev->base
[all...]
/drivers/acpi/apei/
H A DMakefile6 apei-y := apei-base.o hest.o cper.o erst.o
/drivers/gpu/drm/nouveau/
H A Dnouveau_encoder.h44 struct drm_encoder_slave base; member in struct:nouveau_encoder
75 return container_of(slave, struct nouveau_encoder, base);
80 return &enc->base.base;
/drivers/ide/
H A Dqd65xx.h15 #define QD_TIM1_PORT (base)
16 #define QD_CONFIG_PORT (base+0x01)
17 #define QD_TIM2_PORT (base+0x02)
18 #define QD_CONTROL_PORT (base+0x03)
/drivers/mfd/
H A Dtmio_core.c12 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) argument
16 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe);
31 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base) argument
36 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe);
/drivers/misc/sgi-gru/
H A Dgruhandles.h101 static inline void *get_gseg_base_address(void *base, int ctxnum) argument
103 return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum);
106 static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line) argument
108 return (void *)(get_gseg_base_address(base, ctxnum) +
112 static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line) argument
114 return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE +
118 static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum) argument
120 return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE +
124 static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum) argument
126 return (struct gru_tlb_global_handle *)(base
130 get_cbe(void *base, int ctxnum) argument
136 get_tfh(void *base, int ctxnum) argument
142 get_cch(void *base, int ctxnum) argument
[all...]
/drivers/net/wireless/rt2x00/
H A Drt2x00pci.h45 *value = readl(rt2x00dev->csr.base + offset);
52 memcpy_fromio(value, rt2x00dev->csr.base + offset, length);
59 writel(value, rt2x00dev->csr.base + offset);
67 __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);
/drivers/usb/dwc3/
H A Ddwc3-omap.c138 void __iomem *base; member in struct:dwc3_omap
153 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
187 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
189 reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
190 dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
215 void __iomem *base; local
234 dev_err(dev, "missing memory base resource\n");
238 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
239 if (!base) {
270 omap->base
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Completed in 567 milliseconds

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