/drivers/input/misc/ |
H A D | Kconfig | 431 Say Y here if you want to support the built-in real time clock
|
/drivers/media/video/uvc/ |
H A D | uvc_driver.c | 2018 module_param_call(clock, uvc_clock_param_set, uvc_clock_param_get, 2020 MODULE_PARM_DESC(clock, "Video buffers timestamp clock");
|
/drivers/net/ethernet/qlogic/qlge/ |
H A D | qlge_dbg.c | 531 static unsigned int *ql_get_probe(struct ql_adapter *qdev, u32 clock, argument 540 probe = clock
|
/drivers/net/wan/ |
H A D | Kconfig | 81 To change setting such as clock source you will need lmcctl.
|
/drivers/devfreq/ |
H A D | exynos4_bus.c | 7 * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework 33 #include <mach/regs-clock.h> 100 /* 4210 controls clock of mif and voltage of int */ 109 * MIF is the main control knob clock for exynox4x12 MIF/INT 110 * clock and voltage of both mif/int are controlled. 587 /* OPP represents DMC clock + INT voltage */ 592 /* OPP represents MIF clock + MIF voltage */
|
/drivers/gpu/drm/ |
H A D | drm_irq.c | 493 /* Dot clock in Hz: */ 494 dotclock = (u64) crtc->hwmode.clock * 1000; 504 /* Convert scanline length in pixels and video dot clock to 523 DRM_DEBUG("crtc %d: clock %d kHz framedur %d linedur %d, pixeldur %d\n",
|
/drivers/gpu/drm/nouveau/ |
H A D | nv50_crtc.c | 676 OUT_RING (evo, 0x00800000 | mode->clock);
|
/drivers/gpu/drm/radeon/ |
H A D | evergreen.c | 604 u32 sclk; /* engine clock in kHz */ 605 u32 disp_clk; /* display clock in kHz */ 845 pixel_period = 1000000 / (u32)mode->clock; 852 wm.disp_clk = mode->clock; 886 b.full = dfixed_const(mode->clock); 898 b.full = dfixed_const(mode->clock);
|
H A D | radeon_asic.h | 366 void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
|
H A D | si.c | 483 u32 sclk; /* engine clock in kHz */ 484 u32 disp_clk; /* display clock in kHz */ 750 pixel_period = 1000000 / (u32)mode->clock; 757 wm.disp_clk = mode->clock; 794 b.full = dfixed_const(mode->clock); 806 b.full = dfixed_const(mode->clock);
|
/drivers/media/dvb/frontends/ |
H A D | af9013_priv.h | 60 u32 clock; member in struct:af9013_coeff
|
/drivers/media/video/em28xx/ |
H A D | em28xx-dvb.c | 307 .clock = 12000,
|
/drivers/media/video/gspca/ |
H A D | ov519.c | 755 {0x11, 0x83}, /* clock / 3 ? */ 769 * "wait 4096 external clock ... to make sure the sensor is 779 * [5:0] clock divider: 1 793 * = 0 (0x00) ...0.... "Main clock is 48 MHz and 865 * COMF[7] "System clock selection" 866 * = 0 (0x00) 0....... "Use 24 MHz system clock" 1261 * COMM[7:6] "Pixel clock divide option" 1366 * COMM[7:6] "Pixel clock divide option" 1501 { 0x11, 0x00 }, /* Pixel clock = fastest */ 1695 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */ 3266 u8 clock; local [all...] |
/drivers/mfd/ |
H A D | Kconfig | 213 regulators, Dual slot memory card transceivers, real-time clock 249 as clock request handshaking.
|
/drivers/net/can/ |
H A D | at91_can.c | 1261 dev_err(&pdev->dev, "no clock defined\n"); 1298 priv->can.clock.freq = clk_get_rate(clk);
|
H A D | flexcan.c | 883 /* select "bus clock", chip must be disabled */ 939 "clock-frequency", NULL); 947 dev_err(&pdev->dev, "no clock defined\n"); 984 priv->can.clock.freq = clock_freq;
|
H A D | ti_hecc.c | 949 dev_err(&pdev->dev, "No clock available\n"); 954 priv->can.clock.freq = clk_get_rate(priv->clk);
|
/drivers/net/can/softing/ |
H A D | softing_main.c | 666 priv->can.clock.freq = 8000000;
|
/drivers/net/can/usb/ |
H A D | ems_usb.c | 115 * The device actually uses a 16MHz clock to generate the CAN clock 999 dev->can.clock.freq = EMS_USB_ARM7_CLOCK;
|
H A D | esd_usb2.c | 974 priv->can.clock.freq = ESD_USB2_CAN_CLOCK;
|
/drivers/net/can/usb/peak_usb/ |
H A D | pcan_usb_pro.c | 40 /* PCAN-USB Pro adapter internal clock (MHz) */ 678 /* should wait until clock is stabilized */ 993 .clock = {
|
/drivers/net/wireless/ath/ath5k/ |
H A D | ath5k.h | 1497 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1649 /* On AR2315 and AR2317 the PCI clock domain registers
|
/drivers/usb/host/ |
H A D | isp1362-hcd.c | 37 * recovery time (MSCx = 0x7f8c) with a memory clock of 99.53 MHz. 2365 if (isp1362_hcd->board->clock) 2366 isp1362_hcd->board->clock(hcd->self.controller, 1); 2371 /* chip has been reset. First we need to see a clock */ 2417 if (isp1362_hcd->board && isp1362_hcd->board->clock) 2418 isp1362_hcd->board->clock(hcd->self.controller, 0);
|
/drivers/video/ |
H A D | nuc900fb.c | 39 #include <mach/regs-clock.h> 76 /* pixclk is in picseconds. our clock is in Hz*/ 601 printk(KERN_ERR "nuc900-lcd:failed to get lcd clock source\n"); 607 dev_dbg(&pdev->dev, "got and enabled clock\n");
|
/drivers/isdn/hardware/mISDN/ |
H A D | hfcmulti.c | 57 * Bit 0 = 0x001 = Use master clock for this S/T interface 62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock 74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. 75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. 76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. 127 * Give the value of the clock control register (A_ST_CLK_DLY) 133 * Give the value of the clock control register (A_ST_CLK_DLY) 137 * clock: 138 * NOTE: only one clock value must be given once 139 * Selects interface with clock sourc 211 static int clock; variable [all...] |