Searched refs:clock (Results 276 - 300 of 324) sorted by relevance

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/drivers/input/misc/
H A DKconfig431 Say Y here if you want to support the built-in real time clock
/drivers/media/video/uvc/
H A Duvc_driver.c2018 module_param_call(clock, uvc_clock_param_set, uvc_clock_param_get,
2020 MODULE_PARM_DESC(clock, "Video buffers timestamp clock");
/drivers/net/ethernet/qlogic/qlge/
H A Dqlge_dbg.c531 static unsigned int *ql_get_probe(struct ql_adapter *qdev, u32 clock, argument
540 probe = clock
/drivers/net/wan/
H A DKconfig81 To change setting such as clock source you will need lmcctl.
/drivers/devfreq/
H A Dexynos4_bus.c7 * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
33 #include <mach/regs-clock.h>
100 /* 4210 controls clock of mif and voltage of int */
109 * MIF is the main control knob clock for exynox4x12 MIF/INT
110 * clock and voltage of both mif/int are controlled.
587 /* OPP represents DMC clock + INT voltage */
592 /* OPP represents MIF clock + MIF voltage */
/drivers/gpu/drm/
H A Ddrm_irq.c493 /* Dot clock in Hz: */
494 dotclock = (u64) crtc->hwmode.clock * 1000;
504 /* Convert scanline length in pixels and video dot clock to
523 DRM_DEBUG("crtc %d: clock %d kHz framedur %d linedur %d, pixeldur %d\n",
/drivers/gpu/drm/nouveau/
H A Dnv50_crtc.c676 OUT_RING (evo, 0x00800000 | mode->clock);
/drivers/gpu/drm/radeon/
H A Devergreen.c604 u32 sclk; /* engine clock in kHz */
605 u32 disp_clk; /* display clock in kHz */
845 pixel_period = 1000000 / (u32)mode->clock;
852 wm.disp_clk = mode->clock;
886 b.full = dfixed_const(mode->clock);
898 b.full = dfixed_const(mode->clock);
H A Dradeon_asic.h366 void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
H A Dsi.c483 u32 sclk; /* engine clock in kHz */
484 u32 disp_clk; /* display clock in kHz */
750 pixel_period = 1000000 / (u32)mode->clock;
757 wm.disp_clk = mode->clock;
794 b.full = dfixed_const(mode->clock);
806 b.full = dfixed_const(mode->clock);
/drivers/media/dvb/frontends/
H A Daf9013_priv.h60 u32 clock; member in struct:af9013_coeff
/drivers/media/video/em28xx/
H A Dem28xx-dvb.c307 .clock = 12000,
/drivers/media/video/gspca/
H A Dov519.c755 {0x11, 0x83}, /* clock / 3 ? */
769 * "wait 4096 external clock ... to make sure the sensor is
779 * [5:0] clock divider: 1
793 * = 0 (0x00) ...0.... "Main clock is 48 MHz and
865 * COMF[7] "System clock selection"
866 * = 0 (0x00) 0....... "Use 24 MHz system clock"
1261 * COMM[7:6] "Pixel clock divide option"
1366 * COMM[7:6] "Pixel clock divide option"
1501 { 0x11, 0x00 }, /* Pixel clock = fastest */
1695 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3266 u8 clock; local
[all...]
/drivers/mfd/
H A DKconfig213 regulators, Dual slot memory card transceivers, real-time clock
249 as clock request handshaking.
/drivers/net/can/
H A Dat91_can.c1261 dev_err(&pdev->dev, "no clock defined\n");
1298 priv->can.clock.freq = clk_get_rate(clk);
H A Dflexcan.c883 /* select "bus clock", chip must be disabled */
939 "clock-frequency", NULL);
947 dev_err(&pdev->dev, "no clock defined\n");
984 priv->can.clock.freq = clock_freq;
H A Dti_hecc.c949 dev_err(&pdev->dev, "No clock available\n");
954 priv->can.clock.freq = clk_get_rate(priv->clk);
/drivers/net/can/softing/
H A Dsofting_main.c666 priv->can.clock.freq = 8000000;
/drivers/net/can/usb/
H A Dems_usb.c115 * The device actually uses a 16MHz clock to generate the CAN clock
999 dev->can.clock.freq = EMS_USB_ARM7_CLOCK;
H A Desd_usb2.c974 priv->can.clock.freq = ESD_USB2_CAN_CLOCK;
/drivers/net/can/usb/peak_usb/
H A Dpcan_usb_pro.c40 /* PCAN-USB Pro adapter internal clock (MHz) */
678 /* should wait until clock is stabilized */
993 .clock = {
/drivers/net/wireless/ath/ath5k/
H A Dath5k.h1497 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1649 /* On AR2315 and AR2317 the PCI clock domain registers
/drivers/usb/host/
H A Disp1362-hcd.c37 * recovery time (MSCx = 0x7f8c) with a memory clock of 99.53 MHz.
2365 if (isp1362_hcd->board->clock)
2366 isp1362_hcd->board->clock(hcd->self.controller, 1);
2371 /* chip has been reset. First we need to see a clock */
2417 if (isp1362_hcd->board && isp1362_hcd->board->clock)
2418 isp1362_hcd->board->clock(hcd->self.controller, 0);
/drivers/video/
H A Dnuc900fb.c39 #include <mach/regs-clock.h>
76 /* pixclk is in picseconds. our clock is in Hz*/
601 printk(KERN_ERR "nuc900-lcd:failed to get lcd clock source\n");
607 dev_dbg(&pdev->dev, "got and enabled clock\n");
/drivers/isdn/hardware/mISDN/
H A Dhfcmulti.c57 * Bit 0 = 0x001 = Use master clock for this S/T interface
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
133 * Give the value of the clock control register (A_ST_CLK_DLY)
137 * clock:
138 * NOTE: only one clock value must be given once
139 * Selects interface with clock sourc
211 static int clock; variable
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