Searched refs:clock (Results 51 - 75 of 324) sorted by relevance

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/drivers/gpu/drm/radeon/
H A Dr600_audio.c234 * atach the audio codec to the clock source of the encoder
236 void r600_audio_set_clock(struct drm_encoder *encoder, int clock) argument
265 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
274 WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
280 WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
H A Datombios_crtc.c555 u32 adjusted_clock = mode->clock;
557 u32 dp_clock = mode->clock;
571 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
584 if (mode->clock > 200000) /* range limits??? */
597 is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
622 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
624 adjusted_clock = mode->clock * 2;
639 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
660 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
672 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 1
792 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
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H A Dr600_hdmi.c86 static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq) argument
89 *CTS = clock * N / (128 * freq) * 1000;
95 * update the N and CTS parameters for a given pixel clock rate
97 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) argument
106 for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);
110 r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
116 r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
122 r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
329 r600_audio_set_clock(encoder, mode->clock);
335 r600_hdmi_update_ACR(encoder, mode->clock);
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/drivers/i2c/busses/
H A Di2c-elektor.c52 static int clock = 0x1c; variable
103 return (clock);
241 8.25 MHz (PCI/4) clock
243 clock = I2C_PCF_CLK | I2C_PCF_TRNS90;
342 module_param(clock, int, 0);
/drivers/net/can/sja1000/
H A Dsja1000_of_platform.c29 * nxp,external-clock-frequency = <16000000>;
139 prop = of_get_property(np, "nxp,external-clock-frequency", &prop_size);
141 priv->can.clock.freq = *prop / 2;
143 priv->can.clock.freq = SJA1000_OFP_CAN_CLOCK; /* default */
157 prop = of_get_property(np, "nxp,clock-out-frequency", &prop_size);
159 u32 divider = priv->can.clock.freq * 2 / *prop;
179 "reg_base=0x%p irq=%d clock=%d ocr=0x%02x cdr=0x%02x\n",
180 priv->reg_base, dev->irq, priv->can.clock.freq,
/drivers/net/ethernet/adi/
H A Dbfin_mac.h98 struct timecounter clock; member in struct:bfin_mac_local
/drivers/net/wireless/brcm80211/brcmsmac/
H A Dpmu.c34 * Duration for ILP clock frequency measurment in milliseconds
52 /* ILP clock */
55 /* ALP clock on pre-PMU chips */
263 /* query alp/xtal clock frequency */
266 u32 clock = ALP_CLOCK; local
270 return clock;
277 clock = 20000 * 1000;
283 return clock;
/drivers/pcmcia/
H A Dsa11xx_base.c53 * Calculate MECR clock wait states for given CPU clock
148 unsigned int clock = cpufreq_get(0); local
155 sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr)));
158 sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr)));
161 sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr)));
/drivers/sbus/char/
H A Dbbc_i2c.h59 unsigned char own, clock; member in struct:bbc_i2c_bus
/drivers/staging/tidspbridge/include/dspbridge/
H A Dhost_os.h43 #include <plat/clock.h>
/drivers/ata/
H A Dpata_artop.c40 static int clock = 0; variable
109 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
163 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
224 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
262 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
H A Dpata_legacy.c100 u8 clock[2]; member in struct:legacy_data
464 int clock; local
473 /* Read VLB clock strapping */
474 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
477 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
482 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
539 int clock; local
544 /* Get the clock */
552 /* Read VLB clock strapping */
553 clock
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H A Dpata_it821x.c61 * single clock source per channel so mixed UDMA100/133 performance
62 * isn't perfect and we have to pick a clock. Thankfully none of this
92 /* We need these for switching the clock when DMA goes on/off
123 * current clock. These share the same register so are managed by
150 * current clock. Handles the dual clocks and also knows about
193 int clock, altclock; local
199 clock = itdev->want[0][1];
202 clock = itdev->want[1][1];
207 if (clock == ATA_ANY)
208 clock
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/drivers/gpu/drm/i2c/
H A Dsil164_drv.c221 bool duallink = (on && encoder->crtc->mode.clock > 165000);
269 if (mode->clock < 32000)
272 if (mode->clock > 330000 ||
273 (mode->clock > 165000 && !priv->duallink_slave))
285 bool duallink = adjusted_mode->clock > 165000;
/drivers/staging/omapdrm/
H A Domap_connector.c39 mode->clock = timings->pixel_clock;
63 timings->pixel_clock = mode->clock;
223 new_mode->clock = timings.pixel_clock;
233 mode->base.id, mode->name, mode->vrefresh, mode->clock,
300 mode->base.id, mode->name, mode->vrefresh, mode->clock,
/drivers/usb/host/
H A Dr8a66597.h311 u16 clock = 0; local
315 clock = XTAL12;
318 clock = XTAL24;
321 clock = XTAL48;
324 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
328 return clock;
/drivers/ide/
H A Dhpt366.c29 * - use pll if we don't have a clock table. added a 66MHz table that's
51 * Added support for 372N clocking and clock switching. The 372N needs
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
111 * - fold PCI clock detectio
402 u8 clock; /* ATA clock selected */ member in struct:hpt_info
916 enum ata_clock clock; local
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H A Dit821x.c50 * single clock source per channel so mixed UDMA100/133 performance
51 * isn't perfect and we have to pick a clock. Thankfully none of this
79 /* We need these for switching the clock when DMA goes on/off
109 * current clock.
135 * current clock.
174 int clock, altclock, sel = 0; local
178 clock = itdev->want[0][1];
181 clock = itdev->want[1][1];
187 * use the clock needed by the mode with the lower priority
189 if (clock
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/drivers/char/
H A DKconfig271 memory in the real time clock (RTC), which is contained in every PC
303 will get access to the real time clock (or hardware clock) built
306 Every PC has such a clock built in. It can be used to generate
329 will get access to the real time clock (or hardware clock) built
332 Every PC has such a clock built in. It can be used to generate
351 will get access to the real time clock (or hardware clock) built
380 will get access to the real time clock (o
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H A Dmmtimer.c16 * 10/1/04 - Christoph Lameter - provide posix clock CLOCK_SGI_CYCLE
341 t->it.mmtimer.clock = TIMER_OFF;
364 * %MMTIMER_GETRES - Returns the resolution of the clock in femto (10^-15)
367 * %MMTIMER_GETFREQ - Copies the frequency of the clock in Hz to the address
370 * %MMTIMER_GETBITS - Returns the number of bits in the clock's counter
395 case MMTIMER_GETRES: /* resolution of the clock in 10^-15 s */
408 case MMTIMER_GETBITS: /* number of bits in the clock */
412 case MMTIMER_MMAPAVAIL: /* can we mmap the clock into userspace? */
430 * mmtimer_mmap - maps the clock's registers into userspace
434 * Calls remap_pfn_range() to map the clock'
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/drivers/net/ethernet/freescale/
H A Dgianfar_ptp.c2 * PTP 1588 clock using the eTSEC
76 #define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
84 #define COPH (1<<7) /* Generated clock output phase. */
85 #define CIPH (1<<6) /* External oscillator input clock phase */
87 #define BYP (1<<3) /* Bypass drift compensated clock */
89 #define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
124 #define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
137 struct ptp_clock *clock; member in struct:etsects
222 ptp_clock_event(etsects->clock, &event);
233 ptp_clock_event(etsects->clock,
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/drivers/mmc/host/
H A Dsdhci.c193 host->clock = 0;
238 /* force clock reconfiguration */
239 host->clock = 0;
659 if (host->clock)
660 target_timeout += data->timeout_clks / host->clock;
1067 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) argument
1074 if (clock && clock == host->clock)
1080 host->ops->set_clock(host, clock);
1385 unsigned int clock; local
2006 unsigned int clock; local
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/drivers/scsi/
H A Dlasi700.c117 hostdata->clock = LASI700_CLOCK;
120 hostdata->clock = LASI710_CLOCK;
/drivers/video/vermilion/
H A Dvermilion.h247 int (*set_clock) (struct vml_sys * sys, int clock);
248 int (*nearest_clock) (const struct vml_sys * sys, int clock);
/drivers/media/video/s5p-fimc/
H A Dfimc-mdevice.h37 struct clk *clock; member in struct:fimc_camclk_info
47 * @clk_on: sclk_cam clock's state associated with this subdev
63 * @camclk: external sensor clock information

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