1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26#include "drmP.h" 27#include "radeon_drm.h" 28#include "radeon.h" 29#include "radeon_asic.h" 30#include "atom.h" 31 32/* 33 * HDMI color format 34 */ 35enum r600_hdmi_color_format { 36 RGB = 0, 37 YCC_422 = 1, 38 YCC_444 = 2 39}; 40 41/* 42 * IEC60958 status bits 43 */ 44enum r600_hdmi_iec_status_bits { 45 AUDIO_STATUS_DIG_ENABLE = 0x01, 46 AUDIO_STATUS_V = 0x02, 47 AUDIO_STATUS_VCFG = 0x04, 48 AUDIO_STATUS_EMPHASIS = 0x08, 49 AUDIO_STATUS_COPYRIGHT = 0x10, 50 AUDIO_STATUS_NONAUDIO = 0x20, 51 AUDIO_STATUS_PROFESSIONAL = 0x40, 52 AUDIO_STATUS_LEVEL = 0x80 53}; 54 55struct { 56 uint32_t Clock; 57 58 int N_32kHz; 59 int CTS_32kHz; 60 61 int N_44_1kHz; 62 int CTS_44_1kHz; 63 64 int N_48kHz; 65 int CTS_48kHz; 66 67} r600_hdmi_ACR[] = { 68 /* 32kHz 44.1kHz 48kHz */ 69 /* Clock N CTS N CTS N CTS */ 70 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 71 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 72 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 73 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 74 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 75 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 76 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 77 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 78 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 79 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 80 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 81}; 82 83/* 84 * calculate CTS value if it's not found in the table 85 */ 86static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq) 87{ 88 if (*CTS == 0) 89 *CTS = clock * N / (128 * freq) * 1000; 90 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 91 N, *CTS, freq); 92} 93 94/* 95 * update the N and CTS parameters for a given pixel clock rate 96 */ 97static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 98{ 99 struct drm_device *dev = encoder->dev; 100 struct radeon_device *rdev = dev->dev_private; 101 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 102 int CTS; 103 int N; 104 int i; 105 106 for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++); 107 108 CTS = r600_hdmi_ACR[i].CTS_32kHz; 109 N = r600_hdmi_ACR[i].N_32kHz; 110 r600_hdmi_calc_CTS(clock, &CTS, N, 32000); 111 WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12); 112 WREG32(offset+R600_HDMI_32kHz_N, N); 113 114 CTS = r600_hdmi_ACR[i].CTS_44_1kHz; 115 N = r600_hdmi_ACR[i].N_44_1kHz; 116 r600_hdmi_calc_CTS(clock, &CTS, N, 44100); 117 WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12); 118 WREG32(offset+R600_HDMI_44_1kHz_N, N); 119 120 CTS = r600_hdmi_ACR[i].CTS_48kHz; 121 N = r600_hdmi_ACR[i].N_48kHz; 122 r600_hdmi_calc_CTS(clock, &CTS, N, 48000); 123 WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12); 124 WREG32(offset+R600_HDMI_48kHz_N, N); 125} 126 127/* 128 * calculate the crc for a given info frame 129 */ 130static void r600_hdmi_infoframe_checksum(uint8_t packetType, 131 uint8_t versionNumber, 132 uint8_t length, 133 uint8_t *frame) 134{ 135 int i; 136 frame[0] = packetType + versionNumber + length; 137 for (i = 1; i <= length; i++) 138 frame[0] += frame[i]; 139 frame[0] = 0x100 - frame[0]; 140} 141 142/* 143 * build a HDMI Video Info Frame 144 */ 145static void r600_hdmi_videoinfoframe( 146 struct drm_encoder *encoder, 147 enum r600_hdmi_color_format color_format, 148 int active_information_present, 149 uint8_t active_format_aspect_ratio, 150 uint8_t scan_information, 151 uint8_t colorimetry, 152 uint8_t ex_colorimetry, 153 uint8_t quantization, 154 int ITC, 155 uint8_t picture_aspect_ratio, 156 uint8_t video_format_identification, 157 uint8_t pixel_repetition, 158 uint8_t non_uniform_picture_scaling, 159 uint8_t bar_info_data_valid, 160 uint16_t top_bar, 161 uint16_t bottom_bar, 162 uint16_t left_bar, 163 uint16_t right_bar 164) 165{ 166 struct drm_device *dev = encoder->dev; 167 struct radeon_device *rdev = dev->dev_private; 168 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 169 170 uint8_t frame[14]; 171 172 frame[0x0] = 0; 173 frame[0x1] = 174 (scan_information & 0x3) | 175 ((bar_info_data_valid & 0x3) << 2) | 176 ((active_information_present & 0x1) << 4) | 177 ((color_format & 0x3) << 5); 178 frame[0x2] = 179 (active_format_aspect_ratio & 0xF) | 180 ((picture_aspect_ratio & 0x3) << 4) | 181 ((colorimetry & 0x3) << 6); 182 frame[0x3] = 183 (non_uniform_picture_scaling & 0x3) | 184 ((quantization & 0x3) << 2) | 185 ((ex_colorimetry & 0x7) << 4) | 186 ((ITC & 0x1) << 7); 187 frame[0x4] = (video_format_identification & 0x7F); 188 frame[0x5] = (pixel_repetition & 0xF); 189 frame[0x6] = (top_bar & 0xFF); 190 frame[0x7] = (top_bar >> 8); 191 frame[0x8] = (bottom_bar & 0xFF); 192 frame[0x9] = (bottom_bar >> 8); 193 frame[0xA] = (left_bar & 0xFF); 194 frame[0xB] = (left_bar >> 8); 195 frame[0xC] = (right_bar & 0xFF); 196 frame[0xD] = (right_bar >> 8); 197 198 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); 199 /* Our header values (type, version, length) should be alright, Intel 200 * is using the same. Checksum function also seems to be OK, it works 201 * fine for audio infoframe. However calculated value is always lower 202 * by 2 in comparison to fglrx. It breaks displaying anything in case 203 * of TVs that strictly check the checksum. Hack it manually here to 204 * workaround this issue. */ 205 frame[0x0] += 2; 206 207 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0, 208 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 209 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1, 210 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 211 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2, 212 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 213 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3, 214 frame[0xC] | (frame[0xD] << 8)); 215} 216 217/* 218 * build a Audio Info Frame 219 */ 220static void r600_hdmi_audioinfoframe( 221 struct drm_encoder *encoder, 222 uint8_t channel_count, 223 uint8_t coding_type, 224 uint8_t sample_size, 225 uint8_t sample_frequency, 226 uint8_t format, 227 uint8_t channel_allocation, 228 uint8_t level_shift, 229 int downmix_inhibit 230) 231{ 232 struct drm_device *dev = encoder->dev; 233 struct radeon_device *rdev = dev->dev_private; 234 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 235 236 uint8_t frame[11]; 237 238 frame[0x0] = 0; 239 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); 240 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); 241 frame[0x3] = format; 242 frame[0x4] = channel_allocation; 243 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); 244 frame[0x6] = 0; 245 frame[0x7] = 0; 246 frame[0x8] = 0; 247 frame[0x9] = 0; 248 frame[0xA] = 0; 249 250 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); 251 252 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0, 253 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 254 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1, 255 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 256} 257 258/* 259 * test if audio buffer is filled enough to start playing 260 */ 261static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 262{ 263 struct drm_device *dev = encoder->dev; 264 struct radeon_device *rdev = dev->dev_private; 265 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 266 267 return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0; 268} 269 270/* 271 * have buffer status changed since last call? 272 */ 273int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 274{ 275 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 276 int status, result; 277 278 if (!radeon_encoder->hdmi_offset) 279 return 0; 280 281 status = r600_hdmi_is_audio_buffer_filled(encoder); 282 result = radeon_encoder->hdmi_buffer_status != status; 283 radeon_encoder->hdmi_buffer_status = status; 284 285 return result; 286} 287 288/* 289 * write the audio workaround status to the hardware 290 */ 291void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 292{ 293 struct drm_device *dev = encoder->dev; 294 struct radeon_device *rdev = dev->dev_private; 295 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 296 uint32_t offset = radeon_encoder->hdmi_offset; 297 298 if (!offset) 299 return; 300 301 if (!radeon_encoder->hdmi_audio_workaround || 302 r600_hdmi_is_audio_buffer_filled(encoder)) { 303 304 /* disable audio workaround */ 305 WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001); 306 307 } else { 308 /* enable audio workaround */ 309 WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001); 310 } 311} 312 313 314/* 315 * update the info frames with the data from the current display mode 316 */ 317void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 318{ 319 struct drm_device *dev = encoder->dev; 320 struct radeon_device *rdev = dev->dev_private; 321 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 322 323 if (ASIC_IS_DCE5(rdev)) 324 return; 325 326 if (!offset) 327 return; 328 329 r600_audio_set_clock(encoder, mode->clock); 330 331 WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000); 332 WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0); 333 WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000); 334 335 r600_hdmi_update_ACR(encoder, mode->clock); 336 337 WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13); 338 339 WREG32(offset+R600_HDMI_VERSION, 0x202); 340 341 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, 342 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 343 344 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 345 WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF); 346 WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF); 347 WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001); 348 WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001); 349 350 r600_hdmi_audio_workaround(encoder); 351 352 /* audio packets per line, does anyone know how to calc this ? */ 353 WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000); 354} 355 356/* 357 * update settings with current parameters from audio engine 358 */ 359void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 360{ 361 struct drm_device *dev = encoder->dev; 362 struct radeon_device *rdev = dev->dev_private; 363 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 364 365 int channels = r600_audio_channels(rdev); 366 int rate = r600_audio_rate(rdev); 367 int bps = r600_audio_bits_per_sample(rdev); 368 uint8_t status_bits = r600_audio_status_bits(rdev); 369 uint8_t category_code = r600_audio_category_code(rdev); 370 371 uint32_t iec; 372 373 if (!offset) 374 return; 375 376 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 377 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 378 channels, rate, bps); 379 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 380 (int)status_bits, (int)category_code); 381 382 iec = 0; 383 if (status_bits & AUDIO_STATUS_PROFESSIONAL) 384 iec |= 1 << 0; 385 if (status_bits & AUDIO_STATUS_NONAUDIO) 386 iec |= 1 << 1; 387 if (status_bits & AUDIO_STATUS_COPYRIGHT) 388 iec |= 1 << 2; 389 if (status_bits & AUDIO_STATUS_EMPHASIS) 390 iec |= 1 << 3; 391 392 iec |= category_code << 8; 393 394 switch (rate) { 395 case 32000: iec |= 0x3 << 24; break; 396 case 44100: iec |= 0x0 << 24; break; 397 case 88200: iec |= 0x8 << 24; break; 398 case 176400: iec |= 0xc << 24; break; 399 case 48000: iec |= 0x2 << 24; break; 400 case 96000: iec |= 0xa << 24; break; 401 case 192000: iec |= 0xe << 24; break; 402 } 403 404 WREG32(offset+R600_HDMI_IEC60958_1, iec); 405 406 iec = 0; 407 switch (bps) { 408 case 16: iec |= 0x2; break; 409 case 20: iec |= 0x3; break; 410 case 24: iec |= 0xb; break; 411 } 412 if (status_bits & AUDIO_STATUS_V) 413 iec |= 0x5 << 16; 414 415 WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f); 416 417 /* 0x021 or 0x031 sets the audio frame length */ 418 WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31); 419 r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0); 420 421 r600_hdmi_audio_workaround(encoder); 422} 423 424static int r600_hdmi_find_free_block(struct drm_device *dev) 425{ 426 struct radeon_device *rdev = dev->dev_private; 427 struct drm_encoder *encoder; 428 struct radeon_encoder *radeon_encoder; 429 bool free_blocks[3] = { true, true, true }; 430 431 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 432 radeon_encoder = to_radeon_encoder(encoder); 433 switch (radeon_encoder->hdmi_offset) { 434 case R600_HDMI_BLOCK1: 435 free_blocks[0] = false; 436 break; 437 case R600_HDMI_BLOCK2: 438 free_blocks[1] = false; 439 break; 440 case R600_HDMI_BLOCK3: 441 free_blocks[2] = false; 442 break; 443 } 444 } 445 446 if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || 447 rdev->family == CHIP_RS740) { 448 return free_blocks[0] ? R600_HDMI_BLOCK1 : 0; 449 } else if (rdev->family >= CHIP_R600) { 450 if (free_blocks[0]) 451 return R600_HDMI_BLOCK1; 452 else if (free_blocks[1]) 453 return R600_HDMI_BLOCK2; 454 } 455 return 0; 456} 457 458static void r600_hdmi_assign_block(struct drm_encoder *encoder) 459{ 460 struct drm_device *dev = encoder->dev; 461 struct radeon_device *rdev = dev->dev_private; 462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 463 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 464 465 u16 eg_offsets[] = { 466 EVERGREEN_CRTC0_REGISTER_OFFSET, 467 EVERGREEN_CRTC1_REGISTER_OFFSET, 468 EVERGREEN_CRTC2_REGISTER_OFFSET, 469 EVERGREEN_CRTC3_REGISTER_OFFSET, 470 EVERGREEN_CRTC4_REGISTER_OFFSET, 471 EVERGREEN_CRTC5_REGISTER_OFFSET, 472 }; 473 474 if (!dig) { 475 dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n"); 476 return; 477 } 478 479 if (ASIC_IS_DCE5(rdev)) { 480 /* TODO */ 481 } else if (ASIC_IS_DCE4(rdev)) { 482 if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) { 483 dev_err(rdev->dev, "Enabling HDMI on unknown dig\n"); 484 return; 485 } 486 radeon_encoder->hdmi_offset = EVERGREEN_HDMI_BASE + 487 eg_offsets[dig->dig_encoder]; 488 radeon_encoder->hdmi_config_offset = radeon_encoder->hdmi_offset 489 + EVERGREEN_HDMI_CONFIG_OFFSET; 490 } else if (ASIC_IS_DCE3(rdev)) { 491 radeon_encoder->hdmi_offset = dig->dig_encoder ? 492 R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1; 493 if (ASIC_IS_DCE32(rdev)) 494 radeon_encoder->hdmi_config_offset = dig->dig_encoder ? 495 R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1; 496 } else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 || 497 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 498 radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev); 499 } 500} 501 502/* 503 * enable the HDMI engine 504 */ 505void r600_hdmi_enable(struct drm_encoder *encoder) 506{ 507 struct drm_device *dev = encoder->dev; 508 struct radeon_device *rdev = dev->dev_private; 509 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 510 uint32_t offset; 511 512 if (ASIC_IS_DCE5(rdev)) 513 return; 514 515 if (!radeon_encoder->hdmi_offset) { 516 r600_hdmi_assign_block(encoder); 517 if (!radeon_encoder->hdmi_offset) { 518 dev_warn(rdev->dev, "Could not find HDMI block for " 519 "0x%x encoder\n", radeon_encoder->encoder_id); 520 return; 521 } 522 } 523 524 offset = radeon_encoder->hdmi_offset; 525 if (ASIC_IS_DCE5(rdev)) { 526 /* TODO */ 527 } else if (ASIC_IS_DCE4(rdev)) { 528 WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0x1, ~0x1); 529 } else if (ASIC_IS_DCE32(rdev)) { 530 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); 531 } else if (ASIC_IS_DCE3(rdev)) { 532 /* TODO */ 533 } else if (rdev->family >= CHIP_R600) { 534 switch (radeon_encoder->encoder_id) { 535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 536 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, 537 ~AVIVO_TMDSA_CNTL_HDMI_EN); 538 WREG32(offset + R600_HDMI_ENABLE, 0x101); 539 break; 540 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 541 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, 542 ~AVIVO_LVTMA_CNTL_HDMI_EN); 543 WREG32(offset + R600_HDMI_ENABLE, 0x105); 544 break; 545 default: 546 dev_err(rdev->dev, "Unknown HDMI output type\n"); 547 break; 548 } 549 } 550 551 if (rdev->irq.installed 552 && rdev->family != CHIP_RS600 553 && rdev->family != CHIP_RS690 554 && rdev->family != CHIP_RS740 555 && !ASIC_IS_DCE4(rdev)) { 556 /* if irq is available use it */ 557 rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; 558 radeon_irq_set(rdev); 559 560 r600_audio_disable_polling(encoder); 561 } else { 562 /* if not fallback to polling */ 563 r600_audio_enable_polling(encoder); 564 } 565 566 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 567 radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); 568} 569 570/* 571 * disable the HDMI engine 572 */ 573void r600_hdmi_disable(struct drm_encoder *encoder) 574{ 575 struct drm_device *dev = encoder->dev; 576 struct radeon_device *rdev = dev->dev_private; 577 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 578 uint32_t offset; 579 580 if (ASIC_IS_DCE5(rdev)) 581 return; 582 583 offset = radeon_encoder->hdmi_offset; 584 if (!offset) { 585 dev_err(rdev->dev, "Disabling not enabled HDMI\n"); 586 return; 587 } 588 589 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", 590 offset, radeon_encoder->encoder_id); 591 592 /* disable irq */ 593 rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false; 594 radeon_irq_set(rdev); 595 596 /* disable polling */ 597 r600_audio_disable_polling(encoder); 598 599 if (ASIC_IS_DCE5(rdev)) { 600 /* TODO */ 601 } else if (ASIC_IS_DCE4(rdev)) { 602 WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0, ~0x1); 603 } else if (ASIC_IS_DCE32(rdev)) { 604 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); 605 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 606 switch (radeon_encoder->encoder_id) { 607 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 608 WREG32_P(AVIVO_TMDSA_CNTL, 0, 609 ~AVIVO_TMDSA_CNTL_HDMI_EN); 610 WREG32(offset + R600_HDMI_ENABLE, 0); 611 break; 612 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 613 WREG32_P(AVIVO_LVTMA_CNTL, 0, 614 ~AVIVO_LVTMA_CNTL_HDMI_EN); 615 WREG32(offset + R600_HDMI_ENABLE, 0); 616 break; 617 default: 618 dev_err(rdev->dev, "Unknown HDMI output type\n"); 619 break; 620 } 621 } 622 623 radeon_encoder->hdmi_offset = 0; 624 radeon_encoder->hdmi_config_offset = 0; 625} 626