/drivers/pcmcia/ |
H A D | omap_cf.c | 130 u16 control; local 141 control = omap_readw(CF_CONTROL); 287 pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name,
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/drivers/scsi/isci/ |
H A D | port.c | 871 pts_control_value = readl(&iport->port_task_scheduler_registers->control); 873 writel(pts_control_value, &iport->port_task_scheduler_registers->control); 937 pts_control_value = readl(&iport->port_task_scheduler_registers->control); 939 writel(pts_control_value, &iport->port_task_scheduler_registers->control); 1443 pts_control_value = readl(&iport->port_task_scheduler_registers->control); 1445 writel(pts_control_value, &iport->port_task_scheduler_registers->control); 1452 pts_control_value = readl(&iport->port_task_scheduler_registers->control); 1455 writel(pts_control_value, &iport->port_task_scheduler_registers->control);
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/drivers/block/ |
H A D | umem.c | 440 int control = le32_to_cpu(desc->sem_control_bits); local 444 if (!(control & DMASCR_DMA_COMPLETE)) { 445 control = dma_status; 459 (control & DMASCR_TRANSFER_READ) ? 461 if (control & DMASCR_HARD_ERROR) { 468 dump_dmastat(card, control); 954 /* Clear the LED's we control */
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/drivers/media/video/ |
H A D | vino.c | 1842 ctrl = vino->control; 1925 vino->control = ctrl; 1933 u32 ctrl = vino->control; 1938 vino->control = ctrl; 1944 u32 ctrl = vino->control; 1950 vino->control = ctrl; 2468 ctrl = vino->control; 2469 vino->control = ctrl & ~(VINO_CTRL_A_INT | VINO_CTRL_B_INT); 2471 vino->control = ctrl; 3661 struct v4l2_control *control) 3660 vino_g_ctrl(struct file *file, void *__fh, struct v4l2_control *control) argument 3716 vino_s_ctrl(struct file *file, void *__fh, struct v4l2_control *control) argument [all...] |
H A D | v4l2-ctrls.c | 37 /* Pointer to the control reference of the master control */ 39 /* The control corresponding to the v4l2_ext_control ID field. */ 41 /* v4l2_ext_control index of the next control belonging to the 61 the given control ID. The pointer array ends with a NULL pointer. 448 /* Return the control name. */ 601 /* FM Radio Modulator control */ 827 /* Helper function to determine whether the control type is compatible with 877 /* Helper function: copy the current control value back to the caller */ 902 /* Helper function: copy the caller-provider value as the new control valu 2083 v4l2_g_ctrl(struct v4l2_ctrl_handler *hdl, struct v4l2_control *control) argument 2093 v4l2_subdev_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *control) argument 2355 v4l2_s_ctrl(struct v4l2_fh *fh, struct v4l2_ctrl_handler *hdl, struct v4l2_control *control) argument 2370 v4l2_subdev_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *control) argument [all...] |
H A D | soc_camera.c | 1001 icd->control = &client->dev; 1016 icd->control = NULL; 1033 struct device *control = NULL; local 1042 * ov6550. So let's pick 16 as a hint for the control handler. Note 1099 control = to_soc_camera_control(icd); 1100 if (!control || !control->driver || !dev_get_drvdata(control) || 1101 !try_module_get(control->driver->owner)) { 1164 module_put(control [all...] |
/drivers/net/can/cc770/ |
H A D | cc770.c | 211 cc770_write_reg(priv, control, CTRL_CCE | CTRL_INI); 242 cc770_write_reg(priv, control, priv->control_normal_mode); 252 cc770_write_reg(priv, control, (CTRL_CCE | CTRL_INI)); 302 cc770_write_reg(priv, control, CTRL_CCE | CTRL_EAF | CTRL_INI); 329 if (cc770_read_reg(priv, control) & CTRL_EAF) 535 cc770_write_reg(priv, control, CTRL_INI);
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/drivers/net/ethernet/i825xx/ |
H A D | 3c527.c | 767 p->control=0; 776 lp->rx_ring[i-1].p->control |= CONTROL_EOL; 1058 np->control = CONTROL_EOP | CONTROL_EOL; 1067 p->control &= ~CONTROL_EOL; 1213 lp->rx_ring[prev_rx(rx_ring_tail)].p->control |= CONTROL_EOL; 1214 lp->rx_ring[prev_rx(rx_old_tail)].p->control &= ~CONTROL_EOL; 1308 * until we have processed all the control items, but simply count
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/drivers/video/ |
H A D | Kconfig | 35 This framework adds support for low-level control of the video 478 interface (8 bit data, 8 bit control). If you anticipate using 480 GPIO IO address to be used for setting control and data. 504 bool "Apple \"control\" display support" 1075 bool "Support for backlight control" 1079 Say Y here if you want to control the backlight of your display. 1122 bool "Support for backlight control" 1126 Say Y here if you want to control the backlight of your display. 1385 bool "Support for backlight control" 1389 Say Y here if you want to control th [all...] |
H A D | cg6.c | 66 * The FBC could be the frame buffer control 67 * The FHC could is the frame buffer hardware control. 250 u32 control; member in struct:bt_regs 657 sbus_writel(0xff << 24, &bt->control); 659 sbus_writel(0x00 << 24, &bt->control); 661 sbus_writel(0x73 << 24, &bt->control); 663 sbus_writel(0x00 << 24, &bt->control);
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/drivers/net/wireless/ath/ath9k/ |
H A D | xmit.c | 428 memcpy(rates, tx_info->control.rates, sizeof(rates)); 545 memcpy(tx_info->control.rates, rates, sizeof(rates)); 632 rates = tx_info->control.rates; 657 rates = tx_info->control.rates; 768 rix = tx_info->control.rates[0].idx; 769 flags = tx_info->control.rates[0].flags; 947 rates = tx_info->control.rates; 1766 struct ieee80211_sta *sta = tx_info->control.sta; 1767 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 1780 if (tx_info->control [all...] |
/drivers/net/ethernet/apple/ |
H A D | bmac.c | 184 dbdma_st32(&dmap->control, 192 dbdma_st32(&dmap->control, 486 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ 487 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ 1417 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ 1418 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ 1507 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); 1513 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); 1516 out_le32(&rd->control, DBDMA_SET(RUN|WAKE)); 1536 out_le32(&td->control, DBDMA_SE [all...] |
/drivers/usb/host/ |
H A D | u132-hcd.c | 441 retval = u132_read_pcimem(u132, control, &u132->hc_control); 1570 u32 control; local 1576 retval = u132_read_pcimem(u132, control, &control); 1603 u32 control; local 1622 retval = u132_read_pcimem(u132, control, &u132->hc_control); 1625 dev_info(&u132->platform_dev->dev, "resetting from state '%s', control " 1644 retval = u132_write_pcimem(u132, control, u132->hc_control); 1647 retval = u132_read_pcimem(u132, control, &control); 3091 u32 control; local [all...] |
H A D | ohci-at91.c | 73 writel(0, ®s->control); 86 writel(0, ®s->control); 298 * Look at the control requests to the root hub and see if we need to override. 679 (void) ohci_readl (ohci, &ohci->regs->control);
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/drivers/media/video/omap/ |
H A D | omap_vout.c | 1362 ctrl->value = vout->control[0].value; 1380 ctrl->value = vout->control[2].value; 1421 vout->control[0].value = rotation; 1448 vout->control[1].value = color; 1474 vout->control[2].value = mirror; 1892 struct v4l2_control *control; local 1924 /*Initialize the control variables for 1926 control = vout->control; 1927 control[ [all...] |
/drivers/ata/ |
H A D | ata_piix.c | 65 * PIIX4 errata #15 - Must not read control registers 104 ICH5_PCS = 0x92, /* port control and status */ 755 int control = 0; local 770 control |= 1; /* TIME1 enable */ 772 control |= 2; /* IE enable */ 775 control |= 4; /* PPE enable */ 782 control |= 8; /* PIO cycles in PIO0 */ 795 master_data |= (control << 4); 805 master_data |= control; 1596 * and then hand over control t [all...] |
H A D | pata_macio.c | 106 * It has it's own local feature control register as well. 579 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); 625 writel((RUN << 16) | RUN, &dma_regs->control); 627 (void)readl(&dma_regs->control); 640 writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control); 688 writel((FLUSH << 16) | FLUSH, &dma_regs->control); 760 /* Only bother waiting if there's a reset control */ 870 /* Kauai has bus control FCRs directly here */ 970 /* Get Apple bus ID (for clock and ASIC control) */ 1085 /* If chip has local feature control, ma [all...] |
/drivers/media/video/saa7134/ |
H A D | saa7134-video.c | 67 /* Bit 2: Video output clock delay control */ 72 /* Bit 1: Video output clock invert control */ 872 unsigned long base,control,bpl; local 901 control = SAA7134_RS_CONTROL_BURST_16; 903 control |= SAA7134_RS_CONTROL_BSWAP; 905 control |= SAA7134_RS_CONTROL_WSWAP; 910 saa_writel(SAA7134_RS_CONTROL(1),control); 915 saa_writel(SAA7134_RS_CONTROL(1),control); 938 unsigned long base,control,bpl; local 959 control [all...] |
H A D | saa7134-alsa.c | 25 #include <sound/control.h> 446 u32 fmt, control; local 503 control = SAA7134_RS_CONTROL_BURST_16 | 507 control |= SAA7134_RS_CONTROL_BSWAP; 512 saa_writel(SAA7134_RS_CONTROL(6),control); 668 /* I should be able to use runtime->dma_addr in the control
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/drivers/firewire/ |
H A D | core-cdev.c | 1029 /* Macros for decoding the iso packet control header. */ 1043 u32 control; local 1080 if (get_user(control, &p->control)) 1082 u.packet.payload_length = GET_PAYLOAD_LENGTH(control); 1083 u.packet.interrupt = GET_INTERRUPT(control); 1084 u.packet.skip = GET_SKIP(control); 1085 u.packet.tag = GET_TAG(control); 1086 u.packet.sy = GET_SY(control); 1087 u.packet.header_length = GET_HEADER_LENGTH(control); [all...] |
/drivers/net/ethernet/qlogic/qlge/ |
H A D | qlge_mpi.c | 1009 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control) argument 1021 mbcp->mbox_in[1] = control; 1046 static int ql_mb_get_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 *control) argument 1053 *control = 0; 1065 *control = mbcp->mbox_in[1]; 1075 "Failed to get MPI traffic control.\n");
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/drivers/net/wireless/brcm80211/brcmsmac/ |
H A D | ampdu.c | 668 sta = tx_info->control.sta; 1199 rc = rc && (tx_info->control.sta == NULL || ampdu_pars->sta == NULL || 1200 tx_info->control.sta == ampdu_pars->sta); 1214 (tx_info->control.sta == sta || sta == NULL)) 1215 tx_info->control.sta = NULL;
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/drivers/net/wireless/rtlwifi/rtl8192cu/ |
H A D | trx.c | 507 struct ieee80211_sta *sta = info->control.sta = info->control.sta; 512 u8 rate_flag = info->control.rates[0].flags; 572 if (info->control.hw_key) { 573 struct ieee80211_key_conf *keyconf = info->control.hw_key;
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/drivers/cpufreq/ |
H A D | powernow-k7.c | 358 pc.val = (unsigned long) acpi_processor_perf->states[0].control; 365 pc.val = (unsigned long) state->control; 366 pr_debug("acpi: P%d: %d MHz %d mW %d uS control %08x SGTC %d\n", 371 (u32) state->control,
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/drivers/dma/ |
H A D | coh901318.c | 93 i, l, l->control, l->src_addr, l->dst_addr, 246 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) argument 251 writel(control, 309 writel(lli->control, virtbase + COH901318_CX_CTRL + 406 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK; 1051 * Add runtime-specific control on top, make 1125 cohd->head_ctrl = lli->control; 1180 * Here we wrap in the runtime dma control interface
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