Searched refs:pulse (Results 26 - 32 of 32) sorted by relevance

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/drivers/sn/
H A Dioc3.c35 static inline unsigned mcr_pack(unsigned pulse, unsigned sample) argument
37 return (pulse << 10) | (sample << 2);
/drivers/media/rc/
H A Dmceusb.c70 #define MCE_MAX_PULSE_LENGTH 0x7f /* Longest transmittable pulse symbol */
661 dev_info(dev, "RX pulse count: %d\n",
687 dev_info(dev, "Raw IR data, %d pulse/space samples\n", ir->rem);
995 rawir.pulse = ((ir->buf_in[i] & MCE_PULSE_BIT) != 0);
1000 rawir.pulse ? "pulse" : "space",
H A Dwinbond-cir.c360 rawir.pulse = irdata & 0x80 ? false : true;
404 * Y = space (1) or pulse (0)
415 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
907 /* Set TX modulation, 36kHz, 7us pulse width */
/drivers/input/misc/
H A DKconfig334 which can be instructed to pulse or to switch to a particular intensity.
/drivers/net/ethernet/sgi/
H A Dioc3-eth.c225 static inline u32 mcr_pack(u32 pulse, u32 sample) argument
227 return (pulse << 10) | (sample << 2);
/drivers/media/video/cx23885/
H A Dcx23888-ir.c268 * FIFO register pulse width count compuations
274 * of the pulse width counter as read from the FIFO. The two lsb's are
287 * The 2 lsb's of the pulse width timer count are not readable, hence
303 * The 2 lsb's of the pulse width timer count are not readable, hence
316 * The total pulse clock count is an 18 bit pulse width timer count as the most
318 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
709 p->ir_core_data.pulse = u;
996 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1032 v4l2_info(sd, "\tMax measurable pulse widt
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/drivers/media/video/cx25840/
H A Dcx25840-ir.c227 * FIFO register pulse width count compuations
233 * of the pulse width counter as read from the FIFO. The two lsb's are
246 * The 2 lsb's of the pulse width timer count are not readable, hence
265 * The 2 lsb's of the pulse width timer count are not accessible, hence
288 * The 2 lsb's of the pulse width timer count are not readable, hence
301 * The total pulse clock count is an 18 bit pulse width timer count as the most
303 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
712 p->ir_core_data.pulse = u;
1089 v4l2_info(sd, "\tFIFO data on pulse time
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