/drivers/pnp/pnpbios/ |
H A D | core.c | 129 /* extensible set of named bus-specific parameters, 235 pnp_dbg(&dev->dev, "set resources\n"); 310 .set = pnpbios_set_resources,
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/drivers/tty/ |
H A D | moxa.c | 204 unsigned int set, unsigned int clear); 1276 unsigned int set, unsigned int clear) 1289 if (set & TIOCM_RTS) 1291 if (set & TIOCM_DTR) 1563 * 50 - 115200 : the real baud rate set to the port, if 1275 moxa_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) argument
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/drivers/usb/serial/ |
H A D | mos7720.c | 1107 mos7720_port->shadowMCR = UART_MCR_OUT2; /* Must set to enable ints! */ 1574 * This routine is called to set the UART on the device to match 1684 /* set up the MCR register and send it to the mos7720 */ 1691 /* To set hardware flow control to the specified * 1844 unsigned int set, unsigned int clear) 1854 if (set & TIOCM_RTS) 1856 if (set & TIOCM_DTR) 1858 if (set & TIOCM_LOOP) 2073 /* set up serial port private structures */ 1843 mos7720_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) argument
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/drivers/video/intelfb/ |
H A D | intelfbdrv.c | 29 * and the initial video mode must be set with vga=XXX at 423 ERR_MSG("unable to set MTRR\n"); 546 /* set early this option because it could be changed by tv encoder 664 /* set the mem offsets - set them after the already used pages */ 1624 if (cursor->set & FB_CUR_SETPOS) { 1633 if (cursor->set & FB_CUR_SETSIZE) { 1640 if (cursor->set & FB_CUR_SETCMAP) { 1654 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
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/drivers/video/ |
H A D | sm501fb.c | 95 int swap_endian; /* set to swap rgb=>bgr */ 284 /* set gamma values */ 341 /* set r/g/b positions and validate bpp */ 426 * set common registers for framebuffers 498 /* set start of framebuffer to the screen */ 523 * set the geometry registers for specified framebuffer. 539 /* set framebuffer width and display width */ 656 /* set the sync polarities before we check data source */ 674 dev_err(fbi->dev, "failed to set common parameters\n"); 911 * set th [all...] |
H A D | tdfxfb.c | 36 * extensions to the VGA register set go completely unmentioned in the 750 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", 1081 * current cursor state (if enable is set) or we want to query what 1082 * we can do with the cursor (if enable is not set) 1084 if (!cursor->set) 1088 if (cursor->set & FB_CUR_SETCMAP) { 1105 if (cursor->set & FB_CUR_SETPOS) { 1114 if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) { 1217 We rely on the i2c-algo-bit routines to set the pins high before
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/drivers/virtio/ |
H A D | virtio_balloon.c | 282 vb->vdev->config->set(vb->vdev,
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H A D | virtio_mmio.c | 23 * 0x024 W GuestFeaturesSel Set of activated features to set via GuestFeatures 269 /* Queue shouldn't already be set up. */ 373 .set = vm_set,
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/drivers/hwmon/ |
H A D | acpi_power_meter.c | 123 ssize_t (*set)(struct device *dev, member in struct:rw_sensor_template 283 /* Both trip levels must be set */ 663 sensors->dev_attr.store = rw->set;
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H A D | ibmaem.c | 130 ssize_t (*set)(struct device *dev, member in struct:aem_rw_sensor_template 953 sensors->dev_attr.store = rw->set;
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/drivers/infiniband/hw/ipath/ |
H A D | ipath_intr.c | 52 * it's possible that sendbuffererror could have bits set; might 386 * set INIT and DOWN. Down is checked by 643 * (not set in ipath_errormask), or temporarily (set in 669 "%llx set\n", (unsigned long long) 691 * It's not entirely reasonable assuming that the errors set 829 * do this before IBSTATUSCHANGED, in case both bits set in a single 884 * feature that says that writing 0 to a bit in *clear that is set in 908 * still set, and clear "safe" send packet errors related to freeze 978 "Read of interrupt status failed (all bits set)\ [all...] |
/drivers/input/misc/ |
H A D | ati_remote2.c | 98 .set = ati_remote2_set_channel_mask, 107 .set = ati_remote2_set_mode_mask, 697 dev_err(&ar2->udev->dev, "%s - failed to set channel due to error: %d\n",
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/drivers/media/rc/ |
H A D | ene_ir.c | 90 /* A helper to set/clear a bit in register according to boolean variable */ 92 bool set) 94 if (set) 406 /* set sample period*/ 862 /* outside interface: set transmitter mask */ 866 dbg("TX: attempt to set transmitter mask %02x", tx_mask); 880 /* outside interface : set tx carrier */ 886 dbg("TX: attempt to set tx carrier to %d kHz", carrier); 901 /*outside interface : set tx duty cycle */ 91 ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask, bool set) argument
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/drivers/media/video/ |
H A D | ov2640.c | 166 #define REG04_DEF 0x20 /* Always set */ 190 * set to factory default values after which 640 u8 reg, u8 mask, u8 set) 647 val |= set & mask; 802 /* set size win */ 813 /* set cfmt */ 639 ov2640_mask_set(struct i2c_client *client, u8 reg, u8 mask, u8 set) argument
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H A D | ov6650.c | 271 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) argument 285 val |= set; 539 /* set the format we will capture in */
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H A D | ov772x.c | 550 u8 set) 557 val |= set & mask; 626 /* Switch the filter on, set AEC low limit */ 744 * Edge auto strength bit is set by default. 768 * set upper and lower limit 784 * set size format 791 * set DSP_CTRL3 802 * set COM3 820 * set COM7 830 * set COM 547 ov772x_mask_set(struct i2c_client *client, u8 command, u8 mask, u8 set) argument [all...] |
H A D | ov9740.c | 460 static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset) argument 473 val |= set; 670 /* set the format we will capture in */
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H A D | tw9910.c | 337 u8 mask, u8 set) 344 val |= set & mask; 589 * set bus width 628 * set scale 635 * set hsync 856 * set OUTCTR1 336 tw9910_mask_set(struct i2c_client *client, u8 command, u8 mask, u8 set) argument
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/drivers/net/phy/ |
H A D | broadcom.c | 346 * Here, bit 0 _disables_ CLK125 when set. 347 * This bit is set by default. 352 /* Here, bit 0 _enables_ CLK125 when set */ 463 * Select 1000BASE-X register set (primary SerDes) 547 /* Then we can set up the delay. */ 575 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) argument 583 return phy_write(phydev, reg, val | set);
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/drivers/net/wan/ |
H A D | z85230.c | 294 * @set: 1 to set, 0 to clear 302 static void z8530_rtsdtr(struct z8530_channel *c, int set) argument 304 if (set) 1274 * If we can set the low bit of R15 then 1317 * We set the interrupt handler up to discard any events, in case 1348 * We set the interrupt handlers to silence any interrupts. We then 1469 * on the older parts we need to set a flag and 1656 * get the controller set up for the next packet as fast
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/drivers/net/wireless/ath/ath9k/ |
H A D | htc_drv_init.c | 443 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument 449 val |= set;
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H A D | mac.c | 93 * Caution must be taken to ensure to set the frame trigger level based 94 * on the DMA request size. For example if the DMA request size is set to 97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set 622 * If bool is set this will kill any frame which is currently being 626 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) argument 630 if (set) {
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/drivers/net/wireless/b43/ |
H A D | phy_lcn.c | 177 /* TODO: wait for some bit to be set */ 858 u16 set) 862 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); 857 b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, u16 set) argument
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/drivers/net/wireless/p54/ |
H A D | fwio.c | 263 int p54_update_beacon_tim(struct p54_common *priv, u16 aid, bool set) argument 275 tim->entry[0] = cpu_to_le16(set ? (aid | 0x8000) : aid);
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H A D | main.c | 71 bool set) 75 return p54_update_beacon_tim(priv, sta->aid, set); 632 * to get at least one non-null set of channel 758 * we cannot support max_rates * max_rate_tries as we set it 70 p54_set_tim(struct ieee80211_hw *dev, struct ieee80211_sta *sta, bool set) argument
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