Searched refs:CPLB_DIRTY (Results 1 - 5 of 5) sorted by relevance

/arch/blackfin/include/asm/
H A Dcplb.h23 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
35 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
92 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
H A Dpgtable.h63 #define _PAGE_DIRTY (CPLB_DIRTY)
H A Ddef_LPBlackfin.h645 #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ macro
/arch/blackfin/kernel/cplb-mpu/
H A Dcplbmgr.c108 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
289 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
291 data |= CPLB_DIRTY;
360 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
H A Dcplbinit.c53 d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;

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