Searched refs:CPLB_WT (Results 1 - 4 of 4) sorted by relevance

/arch/blackfin/include/asm/
H A Dcplb.h28 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
55 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
91 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
H A Ddef_LPBlackfin.h651 #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ macro
/arch/blackfin/kernel/cplb-mpu/
H A Dcplbmgr.c113 d_data |= CPLB_L1_AOW | CPLB_WT;
289 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
364 d_data |= CPLB_L1_AOW | CPLB_WT;
H A Dcplbinit.c38 d_cache |= CPLB_L1_AOW | CPLB_WT;

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