Searched refs:DMA17_IRQ_STATUS (Results 1 - 4 of 4) sorted by relevance

/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h573 #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ macro
H A DcdefBF538.h950 #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
951 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h786 #define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */ macro
H A DcdefBF54x_base.h1326 #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1327 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)

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