Searched refs:DMA5_START_ADDR (Results 1 - 12 of 12) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h280 #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
281 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
H A DdefBF532.h258 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ macro
/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h516 #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
517 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
H A DdefBF512.h292 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ macro
/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h533 #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
534 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
H A DdefBF522.h292 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ macro
/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h268 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ macro
H A DcdefBF534.h495 #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
496 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h269 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ macro
H A DcdefBF538.h618 #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
619 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h288 #define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */ macro
H A DcdefBF54x_base.h456 #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
457 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)

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