Searched refs:EBIU_SDSTAT (Results 1 - 14 of 14) sorted by relevance

/arch/blackfin/mach-common/
H A Ddpmc_modes.S199 P1.L = lo(EBIU_SDSTAT);
200 P1.H = hi(EBIU_SDSTAT);
/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h478 #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
479 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
H A DdefBF532.h179 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ macro
822 /* EBIU_SDSTAT Masks */
/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h366 #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
367 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
H A DdefBF512.h214 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ macro
1027 /* EBIU_SDSTAT Masks */
/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h383 #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
384 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
H A DdefBF522.h213 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ macro
1028 /* EBIU_SDSTAT Masks */
/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h290 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ macro
1394 /* EBIU_SDSTAT Masks */
H A DcdefBF561.h491 #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
492 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h190 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ macro
1349 /* EBIU_SDSTAT Masks */
H A DcdefBF534.h346 #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
347 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h185 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ macro
1741 /* EBIU_SDSTAT Masks */
H A DcdefBF538.h480 #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
481 #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
/arch/blackfin/kernel/
H A Ddebug-mmrs.c896 D16(EBIU_SDSTAT);

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