Searched refs:ICPLB_ADDR0 (Results 1 - 7 of 7) sorted by relevance

/arch/blackfin/mach-common/
H A Dcache-c.c57 bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
H A Ddpmc_modes.S475 I3.L = lo(ICPLB_ADDR0);
523 PM_PUSH(4, ICPLB_ADDR0)
717 PM_POP(4, ICPLB_ADDR0)
/arch/blackfin/kernel/cplb-nompu/
H A Dcplbmgr.c58 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
/arch/blackfin/include/asm/
H A Dcdef_LPBlackfin.h111 #define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
112 #define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
H A Ddef_LPBlackfin.h323 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability macro
/arch/blackfin/kernel/cplb-mpu/
H A Dcplbmgr.c274 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
/arch/blackfin/kernel/
H A Ddebug-mmrs.c672 D32(ICPLB_ADDR0);

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