Searched refs:MDMA_S0_CONFIG (Results 1 - 14 of 14) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h438 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
439 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
H A DdefBF532.h340 #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ macro
/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h728 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
729 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
H A DdefBF512.h405 #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ macro
/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h745 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
746 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
H A DdefBF522.h405 #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ macro
/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h496 #define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ macro
H A DcdefBF561.h1284 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
1285 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h381 #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ macro
H A DcdefBF534.h707 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
708 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h326 #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ macro
H A DcdefBF538.h1040 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
1041 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h414 #define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */ macro
H A DcdefBF54x_base.h687 #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
688 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)

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