Searched refs:P4 (Results 1 - 4 of 4) sorted by relevance
| /arch/blackfin/mach-common/ |
| H A D | entry.S | 57 P4 = R7; /* Store EXCAUSE */ define
66 R7 = P4;
374 P4.L = LO(IMEM_CONTROL);
375 P4.H = HI(IMEM_CONTROL);
377 R5 = [P4]; /* Control Register*/
380 [P4] = R5;
383 P4.L = LO(DMEM_CONTROL);
384 P4.H = HI(DMEM_CONTROL);
385 R5 = [P4];
388 [P4]
1217 P4 = P3 + P2; define
[all...] |
| H A D | dpmc_modes.S | 90 P4 = R1; define
134 R1 = P4;
289 #define PM_REG9 P4
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| /arch/cris/arch-v10/kernel/ |
| H A D | kgdb.c | 191 registers, P0, P4 and P8, are reserved as zero-registers. A read from
378 registers, P0, P4 and P8, are reserved as zero-registers. A read from
387 P4, CCR, P6, MOF, enumerator in enum:register_name
566 else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
571 /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented,
642 else if (regno == P4 || regno == CCR) {
645 ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short)));
1304 clear.w [reg+0x42] ; Clear P4
1397 clear.w [reg+0x42] ; Clear P4
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| /arch/ia64/kernel/ |
| H A D | unwind_decoder.c | 239 UNW_DEC_SPILL_MASK(P4, dp, arg);
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