Searched refs:SIC_IAR0 (Results 1 - 17 of 17) sorted by relevance

/arch/blackfin/mach-common/
H A Ddpmc_modes.S390 #ifdef SIC_IAR0
391 PM_SYS_PUSH(3, SIC_IAR0)
830 #ifdef SIC_IAR0
833 PM_SYS_POP(3, SIC_IAR0)
H A Dints-priority.c81 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
84 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h26 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
27 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
H A DdefBF532.h29 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
384 /* SIC_IAR0 Masks */
/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
H A DdefBF512.h28 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
648 /* SIC_IAR0 Macros */
/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
H A DdefBF522.h31 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
649 /* SIC_IAR0 Macros */
/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h35 #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ macro
H A DcdefBF561.h36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h26 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
973 /* SIC_IAR0 Macros */
H A DcdefBF534.h30 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
31 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h28 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
H A DcdefBF538.h46 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
47 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
/arch/blackfin/kernel/
H A Ddebug-mmrs.c1459 D32(SIC_IAR0);
/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h48 #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ macro
1511 /* Bit masks for SIC_IAR0 */
H A DcdefBF54x_base.h65 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
66 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)

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