Searched refs:SIC_IWR0 (Results 1 - 16 of 16) sorted by relevance
| /arch/blackfin/mach-bf561/include/mach/ |
| H A D | pll.h | 26 bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
37 *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
|
| H A D | defBF561.h | 45 #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ macro
|
| H A D | cdefBF561.h | 56 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
57 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
|
| /arch/blackfin/mach-common/ |
| H A D | clocks-init.c | 44 #ifdef SIC_IWR0
|
| H A D | pm.c | 36 #ifdef SIC_IWR0
|
| H A D | dpmc_modes.S | 250 #ifdef SIC_IWR0
253 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
419 #ifdef SIC_IWR0
420 PM_SYS_PUSH(1, SIC_IWR0)
803 #ifdef SIC_IWR0
804 PM_SYS_POP(1, SIC_IWR0)
|
| H A D | ints-priority.c | 1087 #ifdef SIC_IWR0
|
| /arch/blackfin/mach-bf518/include/mach/ |
| H A D | cdefBF512.h | 50 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
|
| H A D | defBF512.h | 33 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
|
| /arch/blackfin/mach-bf527/include/mach/ |
| H A D | cdefBF522.h | 50 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
51 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
52 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
53 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
|
| H A D | defBF522.h | 36 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
|
| /arch/blackfin/mach-bf538/include/mach/ |
| H A D | cdefBF538.h | 40 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
41 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
44 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
45 #define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
|
| H A D | defBF538.h | 33 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
|
| /arch/blackfin/kernel/ |
| H A D | debug-mmrs.c | 1489 D32(SIC_IWR0);
|
| /arch/blackfin/mach-bf548/include/mach/ |
| H A D | defBF54x_base.h | 45 #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ macro
1515 /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
|
| H A D | cdefBF54x_base.h | 59 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
60 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
|
Completed in 167 milliseconds