/arch/arm/mach-imx/ |
H A D | cpu-imx31.c | 23 unsigned int rev; member in struct:__anon240 25 { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 }, 26 { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, 27 { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, 28 { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, 29 { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, 30 { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 }, 31 { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 }, 32 { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 }, 33 { .srev = 0x29, .name = "i.MX31L", .rev [all...] |
H A D | cpu-imx25.c | 21 u32 rev; local 23 rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); 24 switch (rev) {
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H A D | cpu-imx35.c | 20 u32 rev; local 22 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); 23 switch (rev) {
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H A D | cpu-imx5.c | 29 u32 rev = readl(iim_base + IIM_SREV) & 0xff; local 31 switch (rev) { 84 u32 rev = readl(iim_base + IIM_SREV) & 0xff; local 86 switch (rev) { 118 u32 rev; local 125 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); 126 rev &= 0xff; 129 if (rev == 0x0) 131 else if (rev == 0x1)
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/arch/arm/mach-kirkwood/ |
H A D | mpp.c | 21 u32 dev, rev; local 23 kirkwood_pcie_id(&dev, &rev); 25 if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) || 28 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) 34 "(dev %#x rev %#x)\n", dev, rev);
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H A D | common.c | 216 u32 dev, rev; local 218 kirkwood_pcie_id(&dev, &rev); 219 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ 324 u32 dev, rev; local 326 kirkwood_pcie_id(&dev, &rev); 397 u32 dev, rev; local 399 kirkwood_pcie_id(&dev, &rev); 402 if (rev == MV88F6281_REV_Z0) 404 else if (rev == MV88F6281_REV_A0) 406 else if (rev 483 u32 dev, rev; local [all...] |
H A D | rd88f6281-setup.c | 81 u32 dev, rev; local 93 kirkwood_pcie_id(&dev, &rev); 94 if (rev == MV88F6281_REV_A0) {
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/arch/arm/mach-mv78xx0/ |
H A D | mpp.c | 21 u32 dev, rev; local 23 mv78xx0_pcie_id(&dev, &rev); 25 if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0) 29 "(dev %#x rev %#x)\n", dev, rev);
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H A D | common.c | 222 u32 dev, rev; local 228 mv78xx0_pcie_id(&dev, &rev); 246 u32 dev, rev; local 252 mv78xx0_pcie_id(&dev, &rev); 344 u32 dev, rev; local 346 mv78xx0_pcie_id(&dev, &rev); 349 if (rev == MV78X00_REV_Z0) 354 if (rev == MV78100_REV_A0) 356 else if (rev == MV78100_REV_A1) 361 if (rev [all...] |
/arch/arm/mach-orion5x/ |
H A D | mpp.c | 22 u32 rev; local 24 orion5x_pcie_id(&dev, &rev); 36 "(dev %#x rev %#x)\n", dev, rev);
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H A D | common.c | 198 u32 dev, rev; local 200 orion5x_pcie_id(&dev, &rev); 225 * Identify device ID and rev from PCIe configuration header space '0'. 227 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) argument 229 orion5x_pcie_id(dev, rev); 232 if (*rev == MV88F5281_REV_D2) { 234 } else if (*rev == MV88F5281_REV_D1) { 236 } else if (*rev == MV88F5281_REV_D0) { 242 if (*rev == MV88F5182_REV_A2) { 248 if (*rev 269 u32 dev, rev; local [all...] |
/arch/mips/ath79/ |
H A D | setup.c | 73 u32 rev = 0; local 81 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 82 rev &= AR71XX_REV_ID_REVISION_MASK; 104 rev = id & AR724X_REV_ID_REVISION_MASK; 110 rev = id & AR724X_REV_ID_REVISION_MASK; 116 rev = id & AR724X_REV_ID_REVISION_MASK; 122 rev = id & AR933X_REV_ID_REVISION_MASK; 128 rev = id & AR933X_REV_ID_REVISION_MASK; 133 rev = id >> AR913X_REV_ID_REVISION_SHIFT; 134 rev [all...] |
/arch/mips/lantiq/ |
H A D | prom.h | 16 unsigned int rev; member in struct:ltq_soc_info
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H A D | prom.c | 23 return soc_info.rev; 66 soc_info.name, soc_info.rev);
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/arch/arm/mach-omap2/ |
H A D | powerdomains3xxx_data.c | 298 unsigned int rev; local 306 rev = omap_rev(); 308 if (rev == OMAP3430_REV_ES1_0) 310 else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 311 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) 313 else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || 314 rev [all...] |
H A D | id.c | 122 u8 dev_type, rev; local 128 rev = (idcode >> 28) & 0x0f; 133 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 293 u8 rev; local 309 * hawkeye and rev. See TRM 1.5.2 Device Identification. 310 * Note that rev does not map directly to our defined processor 315 rev = (idcode >> 28) & 0xff; 320 switch (rev) { 353 switch (rev) { 368 switch(rev) { 434 u8 rev; local [all...] |
H A D | mcbsp.c | 178 if (oh->class->rev < MCBSP_CONFIG_TYPE2) { 187 if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4) 191 if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4) 194 if (oh->class->rev == MCBSP_CONFIG_TYPE3) { 201 } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) { 206 if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
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/arch/arm/mach-ux500/ |
H A D | id.c | 43 unsigned int rev = dbx500_revision(); local 47 if (rev == 0x01) 49 else if (rev >= 0xA0) 50 pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf);
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H A D | cpu.c | 82 unsigned int rev = dbx500_revision(); local 84 if (rev == 0x01) 86 else if (rev >= 0xA0) 88 (rev >> 4) - 0xA + 1, rev & 0xf);
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/arch/arm/mach-ks8695/ |
H A D | cpu.c | 48 unsigned long id, rev; local 51 rev = __raw_readl(KS8695_MISC_VA + KS8695_RID); 53 printk("KS8695 ID=%04lx SubID=%02lx Revision=%02lx\n", (id & DID_ID), (rev & RID_SUBID), (rev & RID_REVISION));
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/arch/x86/kernel/ |
H A D | microcode_amd.c | 85 csig->rev = c->microcode; 86 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); 142 unsigned int leftover_size, int rev, 171 if (mc_hdr->patch_id <= rev) 192 u32 rev, dummy; local 206 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 209 if (rev != mc_amd->hdr.patch_id) { 215 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev); 216 uci->cpu_sig.rev = rev; 141 get_matching_microcode(int cpu, const u8 *ucode_ptr, unsigned int leftover_size, int rev, unsigned int *current_size) argument [all...] |
H A D | microcode_intel.c | 92 unsigned int rev; member in struct:microcode_header_intel 158 csig->rev = c->microcode; 160 cpu_num, csig->sig, csig->pf, csig->rev); 171 update_match_revision(struct microcode_header_intel *mc_header, int rev) argument 173 return (mc_header->rev <= rev) ? 0 : 1; 256 get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev) argument 264 if (!update_match_revision(mc_header, rev)) 315 if (val[1] != mc_intel->hdr.rev) { 317 cpu_num, mc_intel->hdr.rev); [all...] |
/arch/powerpc/kvm/ |
H A D | book3s_hv_rm_mmu.c | 42 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev, argument 56 rev->forw = i; 57 rev->back = head->back; 61 rev->forw = rev->back = pte_index; 71 struct revmap_entry *rev, 81 ptel = rev->guest_rpte |= rcbits; 91 next = real_vmalloc_addr(&kvm->arch.revmap[rev->forw]); 92 prev = real_vmalloc_addr(&kvm->arch.revmap[rev->back]); 93 next->back = rev 70 remove_revmap_chain(struct kvm *kvm, long pte_index, struct revmap_entry *rev, unsigned long hpte_v, unsigned long hpte_r) argument 140 struct revmap_entry *rev; local 353 struct revmap_entry *rev; local 405 struct revmap_entry *rev, *revs[4]; local 521 struct revmap_entry *rev; local 584 struct revmap_entry *rev = NULL; local 751 struct revmap_entry *rev; local [all...] |
/arch/blackfin/ |
H A D | Makefile | 90 rev-$(CONFIG_BF_REV_0_0) := 0.0 91 rev-$(CONFIG_BF_REV_0_1) := 0.1 92 rev-$(CONFIG_BF_REV_0_2) := 0.2 93 rev-$(CONFIG_BF_REV_0_3) := 0.3 94 rev-$(CONFIG_BF_REV_0_4) := 0.4 95 rev-$(CONFIG_BF_REV_0_5) := 0.5 96 rev-$(CONFIG_BF_REV_0_6) := 0.6 97 rev-$(CONFIG_BF_REV_NONE) := none 98 rev-$(CONFIG_BF_REV_ANY) := any 100 CPU_REV := $(cpu-y)-$(rev [all...] |
/arch/m68k/mvme16x/ |
H A D | config.c | 100 unsigned char rev = *(unsigned char *)MVME162_VERSION_REG; local 103 rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : ""); 105 rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : ""); 107 rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : ""); 312 printk ("\nBRD_ID: %s BUG %x.%x %02x/%02x/%02x\n", id, p->rev>>4, 313 p->rev&0xf, p->yr, p->mth, p->day); 316 unsigned char rev = *(unsigned char *)MVME162_VERSION_REG; local 318 mvme16x_config = rev | MVME16x_CONFIG_GOT_SCCA; 322 rev & MVME16x_CONFIG_GOT_FPU ? "" : "LC"); 324 rev [all...] |