1/*
2 * linux/arch/arm/mach-omap2/id.c
3 *
4 * OMAP2 CPU identification code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21
22#include <asm/cputype.h>
23
24#include "common.h"
25#include <plat/cpu.h>
26
27#include <mach/id.h>
28
29#include "control.h"
30
31static unsigned int omap_revision;
32static const char *cpu_rev;
33u32 omap_features;
34
35unsigned int omap_rev(void)
36{
37	return omap_revision;
38}
39EXPORT_SYMBOL(omap_rev);
40
41int omap_type(void)
42{
43	u32 val = 0;
44
45	if (cpu_is_omap24xx()) {
46		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
47	} else if (cpu_is_am33xx()) {
48		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
49	} else if (cpu_is_omap34xx()) {
50		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
51	} else if (cpu_is_omap44xx()) {
52		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
53	} else {
54		pr_err("Cannot detect omap type!\n");
55		goto out;
56	}
57
58	val &= OMAP2_DEVICETYPE_MASK;
59	val >>= 8;
60
61out:
62	return val;
63}
64EXPORT_SYMBOL(omap_type);
65
66
67/*----------------------------------------------------------------------------*/
68
69#define OMAP_TAP_IDCODE		0x0204
70#define OMAP_TAP_DIE_ID_0	0x0218
71#define OMAP_TAP_DIE_ID_1	0x021C
72#define OMAP_TAP_DIE_ID_2	0x0220
73#define OMAP_TAP_DIE_ID_3	0x0224
74
75#define OMAP_TAP_DIE_ID_44XX_0	0x0200
76#define OMAP_TAP_DIE_ID_44XX_1	0x0208
77#define OMAP_TAP_DIE_ID_44XX_2	0x020c
78#define OMAP_TAP_DIE_ID_44XX_3	0x0210
79
80#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))
81
82struct omap_id {
83	u16	hawkeye;	/* Silicon type (Hawkeye id) */
84	u8	dev;		/* Device type from production_id reg */
85	u32	type;		/* Combined type id copied to omap_revision */
86};
87
88/* Register values to detect the OMAP version */
89static struct omap_id omap_ids[] __initdata = {
90	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
91	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
92	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
93	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
94	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
95	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
96};
97
98static void __iomem *tap_base;
99static u16 tap_prod_id;
100
101void omap_get_die_id(struct omap_die_id *odi)
102{
103	if (cpu_is_omap44xx()) {
104		odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
105		odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
106		odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
107		odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
108
109		return;
110	}
111	odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
112	odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
113	odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
114	odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
115}
116
117void __init omap2xxx_check_revision(void)
118{
119	int i, j;
120	u32 idcode, prod_id;
121	u16 hawkeye;
122	u8  dev_type, rev;
123	struct omap_die_id odi;
124
125	idcode = read_tap_reg(OMAP_TAP_IDCODE);
126	prod_id = read_tap_reg(tap_prod_id);
127	hawkeye = (idcode >> 12) & 0xffff;
128	rev = (idcode >> 28) & 0x0f;
129	dev_type = (prod_id >> 16) & 0x0f;
130	omap_get_die_id(&odi);
131
132	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
133		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
134	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
135	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
136		 odi.id_1, (odi.id_1 >> 28) & 0xf);
137	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
138	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
139	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
140		 prod_id, dev_type);
141
142	/* Check hawkeye ids */
143	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
144		if (hawkeye == omap_ids[i].hawkeye)
145			break;
146	}
147
148	if (i == ARRAY_SIZE(omap_ids)) {
149		printk(KERN_ERR "Unknown OMAP CPU id\n");
150		return;
151	}
152
153	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
154		if (dev_type == omap_ids[j].dev)
155			break;
156	}
157
158	if (j == ARRAY_SIZE(omap_ids)) {
159		printk(KERN_ERR "Unknown OMAP device type. "
160				"Handling it as OMAP%04x\n",
161				omap_ids[i].type >> 16);
162		j = i;
163	}
164
165	pr_info("OMAP%04x", omap_rev() >> 16);
166	if ((omap_rev() >> 8) & 0x0f)
167		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
168	pr_info("\n");
169}
170
171#define OMAP3_SHOW_FEATURE(feat)		\
172	if (omap3_has_ ##feat())		\
173		printk(#feat" ");
174
175static void __init omap3_cpuinfo(void)
176{
177	const char *cpu_name;
178
179	/*
180	 * OMAP3430 and OMAP3530 are assumed to be same.
181	 *
182	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
183	 * on available features. Upon detection, update the CPU id
184	 * and CPU class bits.
185	 */
186	if (cpu_is_omap3630()) {
187		cpu_name = "OMAP3630";
188	} else if (cpu_is_omap3517()) {
189		/* AM35xx devices */
190		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
191	} else if (cpu_is_ti816x()) {
192		cpu_name = "TI816X";
193	} else if (cpu_is_am335x()) {
194		cpu_name =  "AM335X";
195	} else if (cpu_is_ti814x()) {
196		cpu_name = "TI814X";
197	} else if (omap3_has_iva() && omap3_has_sgx()) {
198		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
199		cpu_name = "OMAP3430/3530";
200	} else if (omap3_has_iva()) {
201		cpu_name = "OMAP3525";
202	} else if (omap3_has_sgx()) {
203		cpu_name = "OMAP3515";
204	} else {
205		cpu_name = "OMAP3503";
206	}
207
208	/* Print verbose information */
209	pr_info("%s ES%s (", cpu_name, cpu_rev);
210
211	OMAP3_SHOW_FEATURE(l2cache);
212	OMAP3_SHOW_FEATURE(iva);
213	OMAP3_SHOW_FEATURE(sgx);
214	OMAP3_SHOW_FEATURE(neon);
215	OMAP3_SHOW_FEATURE(isp);
216	OMAP3_SHOW_FEATURE(192mhz_clk);
217
218	printk(")\n");
219}
220
221#define OMAP3_CHECK_FEATURE(status,feat)				\
222	if (((status & OMAP3_ ##feat## _MASK) 				\
223		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
224		omap_features |= OMAP3_HAS_ ##feat;			\
225	}
226
227void __init omap3xxx_check_features(void)
228{
229	u32 status;
230
231	omap_features = 0;
232
233	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
234
235	OMAP3_CHECK_FEATURE(status, L2CACHE);
236	OMAP3_CHECK_FEATURE(status, IVA);
237	OMAP3_CHECK_FEATURE(status, SGX);
238	OMAP3_CHECK_FEATURE(status, NEON);
239	OMAP3_CHECK_FEATURE(status, ISP);
240	if (cpu_is_omap3630())
241		omap_features |= OMAP3_HAS_192MHZ_CLK;
242	if (cpu_is_omap3430() || cpu_is_omap3630())
243		omap_features |= OMAP3_HAS_IO_WAKEUP;
244	if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
245	    omap_rev() == OMAP3430_REV_ES3_1_2)
246		omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
247
248	omap_features |= OMAP3_HAS_SDRC;
249
250	/*
251	 * TODO: Get additional info (where applicable)
252	 *       e.g. Size of L2 cache.
253	 */
254
255	omap3_cpuinfo();
256}
257
258void __init omap4xxx_check_features(void)
259{
260	u32 si_type;
261
262	if (cpu_is_omap443x())
263		omap_features |= OMAP4_HAS_MPU_1GHZ;
264
265
266	if (cpu_is_omap446x()) {
267		si_type =
268			read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
269		switch ((si_type & (3 << 16)) >> 16) {
270		case 2:
271			/* High performance device */
272			omap_features |= OMAP4_HAS_MPU_1_5GHZ;
273			break;
274		case 1:
275		default:
276			/* Standard device */
277			omap_features |= OMAP4_HAS_MPU_1_2GHZ;
278			break;
279		}
280	}
281}
282
283void __init ti81xx_check_features(void)
284{
285	omap_features = OMAP3_HAS_NEON;
286	omap3_cpuinfo();
287}
288
289void __init omap3xxx_check_revision(void)
290{
291	u32 cpuid, idcode;
292	u16 hawkeye;
293	u8 rev;
294
295	/*
296	 * We cannot access revision registers on ES1.0.
297	 * If the processor type is Cortex-A8 and the revision is 0x0
298	 * it means its Cortex r0p0 which is 3430 ES1.0.
299	 */
300	cpuid = read_cpuid(CPUID_ID);
301	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
302		omap_revision = OMAP3430_REV_ES1_0;
303		cpu_rev = "1.0";
304		return;
305	}
306
307	/*
308	 * Detection for 34xx ES2.0 and above can be done with just
309	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
310	 * Note that rev does not map directly to our defined processor
311	 * revision numbers as ES1.0 uses value 0.
312	 */
313	idcode = read_tap_reg(OMAP_TAP_IDCODE);
314	hawkeye = (idcode >> 12) & 0xffff;
315	rev = (idcode >> 28) & 0xff;
316
317	switch (hawkeye) {
318	case 0xb7ae:
319		/* Handle 34xx/35xx devices */
320		switch (rev) {
321		case 0: /* Take care of early samples */
322		case 1:
323			omap_revision = OMAP3430_REV_ES2_0;
324			cpu_rev = "2.0";
325			break;
326		case 2:
327			omap_revision = OMAP3430_REV_ES2_1;
328			cpu_rev = "2.1";
329			break;
330		case 3:
331			omap_revision = OMAP3430_REV_ES3_0;
332			cpu_rev = "3.0";
333			break;
334		case 4:
335			omap_revision = OMAP3430_REV_ES3_1;
336			cpu_rev = "3.1";
337			break;
338		case 7:
339		/* FALLTHROUGH */
340		default:
341			/* Use the latest known revision as default */
342			omap_revision = OMAP3430_REV_ES3_1_2;
343			cpu_rev = "3.1.2";
344		}
345		break;
346	case 0xb868:
347		/*
348		 * Handle OMAP/AM 3505/3517 devices
349		 *
350		 * Set the device to be OMAP3517 here. Actual device
351		 * is identified later based on the features.
352		 */
353		switch (rev) {
354		case 0:
355			omap_revision = OMAP3517_REV_ES1_0;
356			cpu_rev = "1.0";
357			break;
358		case 1:
359		/* FALLTHROUGH */
360		default:
361			omap_revision = OMAP3517_REV_ES1_1;
362			cpu_rev = "1.1";
363		}
364		break;
365	case 0xb891:
366		/* Handle 36xx devices */
367
368		switch(rev) {
369		case 0: /* Take care of early samples */
370			omap_revision = OMAP3630_REV_ES1_0;
371			cpu_rev = "1.0";
372			break;
373		case 1:
374			omap_revision = OMAP3630_REV_ES1_1;
375			cpu_rev = "1.1";
376			break;
377		case 2:
378		/* FALLTHROUGH */
379		default:
380			omap_revision = OMAP3630_REV_ES1_2;
381			cpu_rev = "1.2";
382		}
383		break;
384	case 0xb81e:
385		switch (rev) {
386		case 0:
387			omap_revision = TI8168_REV_ES1_0;
388			cpu_rev = "1.0";
389			break;
390		case 1:
391		/* FALLTHROUGH */
392		default:
393			omap_revision = TI8168_REV_ES1_1;
394			cpu_rev = "1.1";
395			break;
396		}
397		break;
398	case 0xb944:
399		omap_revision = AM335X_REV_ES1_0;
400		cpu_rev = "1.0";
401		break;
402	case 0xb8f2:
403		switch (rev) {
404		case 0:
405		/* FALLTHROUGH */
406		case 1:
407			omap_revision = TI8148_REV_ES1_0;
408			cpu_rev = "1.0";
409			break;
410		case 2:
411			omap_revision = TI8148_REV_ES2_0;
412			cpu_rev = "2.0";
413			break;
414		case 3:
415		/* FALLTHROUGH */
416		default:
417			omap_revision = TI8148_REV_ES2_1;
418			cpu_rev = "2.1";
419			break;
420		}
421		break;
422	default:
423		/* Unknown default to latest silicon rev as default */
424		omap_revision = OMAP3630_REV_ES1_2;
425		cpu_rev = "1.2";
426		pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
427	}
428}
429
430void __init omap4xxx_check_revision(void)
431{
432	u32 idcode;
433	u16 hawkeye;
434	u8 rev;
435
436	/*
437	 * The IC rev detection is done with hawkeye and rev.
438	 * Note that rev does not map directly to defined processor
439	 * revision numbers as ES1.0 uses value 0.
440	 */
441	idcode = read_tap_reg(OMAP_TAP_IDCODE);
442	hawkeye = (idcode >> 12) & 0xffff;
443	rev = (idcode >> 28) & 0xf;
444
445	/*
446	 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
447	 * Use ARM register to detect the correct ES version
448	 */
449	if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
450		idcode = read_cpuid(CPUID_ID);
451		rev = (idcode & 0xf) - 1;
452	}
453
454	switch (hawkeye) {
455	case 0xb852:
456		switch (rev) {
457		case 0:
458			omap_revision = OMAP4430_REV_ES1_0;
459			break;
460		case 1:
461		default:
462			omap_revision = OMAP4430_REV_ES2_0;
463		}
464		break;
465	case 0xb95c:
466		switch (rev) {
467		case 3:
468			omap_revision = OMAP4430_REV_ES2_1;
469			break;
470		case 4:
471			omap_revision = OMAP4430_REV_ES2_2;
472			break;
473		case 6:
474		default:
475			omap_revision = OMAP4430_REV_ES2_3;
476		}
477		break;
478	case 0xb94e:
479		switch (rev) {
480		case 0:
481		default:
482			omap_revision = OMAP4460_REV_ES1_0;
483			break;
484		}
485		break;
486	case 0xb975:
487		switch (rev) {
488		case 0:
489		default:
490			omap_revision = OMAP4470_REV_ES1_0;
491			break;
492		}
493		break;
494	default:
495		/* Unknown default to latest silicon rev as default */
496		omap_revision = OMAP4430_REV_ES2_3;
497	}
498
499	pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
500		((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
501}
502
503/*
504 * Set up things for map_io and processor detection later on. Gets called
505 * pretty much first thing from board init. For multi-omap, this gets
506 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
507 * detect the exact revision later on in omap2_detect_revision() once map_io
508 * is done.
509 */
510void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
511{
512	omap_revision = omap2_globals->class;
513	tap_base = omap2_globals->tap;
514
515	if (cpu_is_omap34xx())
516		tap_prod_id = 0x0210;
517	else
518		tap_prod_id = 0x0208;
519}
520