Searched refs:BLC_PWM_CTL (Results 1 - 11 of 11) sorted by relevance
/drivers/gpu/drm/i915/ |
H A D | intel_panel.c | 125 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; 146 val = I915_READ(BLC_PWM_CTL); 151 I915_WRITE(BLC_PWM_CTL, 200 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 242 tmp = I915_READ(BLC_PWM_CTL); 246 I915_WRITE(BLC_PWM_CTL, tmp | level);
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H A D | intel_opregion.c | 180 u32 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
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H A D | i915_suspend.c | 636 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 756 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
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H A D | i915_reg.h | 1702 #define BLC_PWM_CTL 0x61254 macro
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/drivers/gpu/drm/gma500/ |
H A D | psb_intel_lvds.c | 77 ret = REG_READ(BLC_PWM_CTL); 89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); 150 /*BLC_PWM_CTL Should be initiated while backlight device init*/ 159 REG_WRITE(BLC_PWM_CTL, 201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); 203 REG_WRITE(BLC_PWM_CTL, 281 lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 323 REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); 452 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
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H A D | cdv_intel_lvds.c | 75 retval = ((REG_READ(BLC_PWM_CTL) & 136 /*BLC_PWM_CTL Should be initiated while backlight device init*/ 145 REG_WRITE(BLC_PWM_CTL, 183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 184 REG_WRITE(BLC_PWM_CTL, 331 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
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H A D | oaktrail_device.c | 75 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 92 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 133 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 242 regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 371 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
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H A D | cdv_device.c | 273 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 346 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
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H A D | oaktrail_lvds.c | 176 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 189 ret = ((REG_READ(BLC_PWM_CTL) &
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H A D | psb_device.c | 97 REG_WRITE(BLC_PWM_CTL,
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H A D | psb_intel_reg.h | 92 #define BLC_PWM_CTL 0x61254 macro 800 /* #define BLC_PWM_CTL 0x61254 */
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