Searched refs:CSR14 (Results 1 - 16 of 16) sorted by relevance

/drivers/net/ethernet/dec/tulip/
H A Dpnic2.c31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
65 * CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> MODE/PORT
108 csr14 = (ioread32(ioaddr + CSR14) & 0xfff0ee39);
153 iowrite32(csr14, ioaddr + CSR14);
182 csr12, csr5, ioread32(ioaddr + CSR14));
241 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
242 iowrite32(csr14,ioaddr + CSR14);
290 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f);
291 iowrite32(csr14,ioaddr + CSR14);
392 csr14 = (ioread32(ioaddr + CSR14)
[all...]
H A D21142.c37 int csr14 = ioread32(ioaddr + CSR14);
80 iowrite32(0x0003FFFF, ioaddr + CSR14);
88 iowrite32(0x0003FFFF, ioaddr + CSR14);
126 iowrite32(csr14, ioaddr + CSR14);
144 int csr14 = ioread32(ioaddr + CSR14);
234 iowrite32(csr14 & ~0x080, ioaddr + CSR14);
251 iowrite32(0x0003FF7F, ioaddr + CSR14);
H A Dtimer.c32 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
H A Dtulip_core.c343 iowrite32(addr_low, ioaddr + CSR14);
345 iowrite32(addr_high, ioaddr + CSR14);
423 iowrite32(0x0000, ioaddr + CSR14);
439 iowrite32(0x0000, ioaddr + CSR14);
557 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
933 int csr14 = ioread32 (ioaddr + CSR14);
1118 iowrite32(mc_filter[0], ioaddr + CSR14);
1120 iowrite32(mc_filter[1], ioaddr + CSR14);
1753 iowrite32(0x0000, ioaddr + CSR14);
1761 iowrite32(0x0000, ioaddr + CSR14);
[all...]
H A Dmedia.c218 iowrite32(csr14val, ioaddr + CSR14);
231 iowrite32(csr14val, ioaddr + CSR14);
H A Dtulip.h120 CSR14 = 0x70, enumerator in enum:tulip_offsets
H A Dde2104x.c157 CSR14 = 0x70, enumerator in enum:__anon2158
929 dw32(CSR14, de->media[media].csr14);
946 dr32(CSR13), dr32(CSR14), dr32(CSR15));
H A Dde4x5.h631 #define CSR14 0x0003ff7f /* Autonegotiation disabled */ macro
H A Dxircom_cb.c61 #define CSR14 0x70 macro
H A Dde4x5.c4686 lp->cache.csr14 = CSR14;
4763 lp->cache.csr14 = CSR14;
/drivers/net/wireless/rt2x00/
H A Drt2400pci.c307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
309 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
648 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
652 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
704 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
708 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
839 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
848 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1184 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1186 rt2x00pci_register_write(rt2x00dev, CSR14, re
[all...]
H A Drt2500pci.c313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
315 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
738 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
742 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
794 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
798 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
932 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
941 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1337 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1339 rt2x00pci_register_write(rt2x00dev, CSR14, re
[all...]
H A Drt2400pci.h201 * CSR14: Synchronization control register.
211 #define CSR14 0x0038 macro
H A Drt2500pci.h278 * CSR14: Synchronization control register.
288 #define CSR14 0x0038 macro
/drivers/net/ethernet/amd/
H A Dariadne.h74 #define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */ macro
H A Dariadne.c447 lance->RAP = CSR14; /* Physical Address Register, PADR[47:32] */

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