/drivers/net/ethernet/dec/tulip/ |
H A D | pnic2.c | 31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set) 65 * CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> MODE/PORT 108 csr14 = (ioread32(ioaddr + CSR14) & 0xfff0ee39); 153 iowrite32(csr14, ioaddr + CSR14); 182 csr12, csr5, ioread32(ioaddr + CSR14)); 241 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f); 242 iowrite32(csr14,ioaddr + CSR14); 290 csr14 = (ioread32(ioaddr + CSR14) & 0xffffff7f); 291 iowrite32(csr14,ioaddr + CSR14); 392 csr14 = (ioread32(ioaddr + CSR14) [all...] |
H A D | 21142.c | 37 int csr14 = ioread32(ioaddr + CSR14); 80 iowrite32(0x0003FFFF, ioaddr + CSR14); 88 iowrite32(0x0003FFFF, ioaddr + CSR14); 126 iowrite32(csr14, ioaddr + CSR14); 144 int csr14 = ioread32(ioaddr + CSR14); 234 iowrite32(csr14 & ~0x080, ioaddr + CSR14); 251 iowrite32(0x0003FF7F, ioaddr + CSR14);
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H A D | timer.c | 32 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
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H A D | tulip_core.c | 343 iowrite32(addr_low, ioaddr + CSR14); 345 iowrite32(addr_high, ioaddr + CSR14); 423 iowrite32(0x0000, ioaddr + CSR14); 439 iowrite32(0x0000, ioaddr + CSR14); 557 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), 933 int csr14 = ioread32 (ioaddr + CSR14); 1118 iowrite32(mc_filter[0], ioaddr + CSR14); 1120 iowrite32(mc_filter[1], ioaddr + CSR14); 1753 iowrite32(0x0000, ioaddr + CSR14); 1761 iowrite32(0x0000, ioaddr + CSR14); [all...] |
H A D | media.c | 218 iowrite32(csr14val, ioaddr + CSR14); 231 iowrite32(csr14val, ioaddr + CSR14);
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H A D | tulip.h | 120 CSR14 = 0x70, enumerator in enum:tulip_offsets
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H A D | de2104x.c | 157 CSR14 = 0x70, enumerator in enum:__anon2158 929 dw32(CSR14, de->media[media].csr14); 946 dr32(CSR13), dr32(CSR14), dr32(CSR15));
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H A D | de4x5.h | 631 #define CSR14 0x0003ff7f /* Autonegotiation disabled */ macro
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H A D | xircom_cb.c | 61 #define CSR14 0x70 macro
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H A D | de4x5.c | 4686 lp->cache.csr14 = CSR14; 4763 lp->cache.csr14 = CSR14;
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/drivers/net/wireless/rt2x00/ |
H A D | rt2400pci.c | 307 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 309 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 648 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 652 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 704 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 708 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 839 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 848 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1184 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 1186 rt2x00pci_register_write(rt2x00dev, CSR14, re [all...] |
H A D | rt2500pci.c | 313 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 315 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 738 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 742 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 794 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 798 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 932 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 941 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1337 rt2x00pci_register_read(rt2x00dev, CSR14, ®); 1339 rt2x00pci_register_write(rt2x00dev, CSR14, re [all...] |
H A D | rt2400pci.h | 201 * CSR14: Synchronization control register. 211 #define CSR14 0x0038 macro
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H A D | rt2500pci.h | 278 * CSR14: Synchronization control register. 288 #define CSR14 0x0038 macro
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/drivers/net/ethernet/amd/ |
H A D | ariadne.h | 74 #define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */ macro
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H A D | ariadne.c | 447 lance->RAP = CSR14; /* Physical Address Register, PADR[47:32] */
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