1/* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the 17 Free Software Foundation, Inc., 18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21/* 22 Module: rt2400pci 23 Abstract: Data structures and registers for the rt2400pci module. 24 Supported chipsets: RT2460. 25 */ 26 27#ifndef RT2400PCI_H 28#define RT2400PCI_H 29 30/* 31 * RF chip defines. 32 */ 33#define RF2420 0x0000 34#define RF2421 0x0001 35 36/* 37 * Signal information. 38 * Default offset is required for RSSI <-> dBm conversion. 39 */ 40#define DEFAULT_RSSI_OFFSET 100 41 42/* 43 * Register layout information. 44 */ 45#define CSR_REG_BASE 0x0000 46#define CSR_REG_SIZE 0x014c 47#define EEPROM_BASE 0x0000 48#define EEPROM_SIZE 0x0100 49#define BBP_BASE 0x0000 50#define BBP_SIZE 0x0020 51#define RF_BASE 0x0004 52#define RF_SIZE 0x000c 53 54/* 55 * Number of TX queues. 56 */ 57#define NUM_TX_QUEUES 2 58 59/* 60 * Control/Status Registers(CSR). 61 * Some values are set in TU, whereas 1 TU == 1024 us. 62 */ 63 64/* 65 * CSR0: ASIC revision number. 66 */ 67#define CSR0 0x0000 68#define CSR0_REVISION FIELD32(0x0000ffff) 69 70/* 71 * CSR1: System control register. 72 * SOFT_RESET: Software reset, 1: reset, 0: normal. 73 * BBP_RESET: Hardware reset, 1: reset, 0, release. 74 * HOST_READY: Host ready after initialization. 75 */ 76#define CSR1 0x0004 77#define CSR1_SOFT_RESET FIELD32(0x00000001) 78#define CSR1_BBP_RESET FIELD32(0x00000002) 79#define CSR1_HOST_READY FIELD32(0x00000004) 80 81/* 82 * CSR2: System admin status register (invalid). 83 */ 84#define CSR2 0x0008 85 86/* 87 * CSR3: STA MAC address register 0. 88 */ 89#define CSR3 0x000c 90#define CSR3_BYTE0 FIELD32(0x000000ff) 91#define CSR3_BYTE1 FIELD32(0x0000ff00) 92#define CSR3_BYTE2 FIELD32(0x00ff0000) 93#define CSR3_BYTE3 FIELD32(0xff000000) 94 95/* 96 * CSR4: STA MAC address register 1. 97 */ 98#define CSR4 0x0010 99#define CSR4_BYTE4 FIELD32(0x000000ff) 100#define CSR4_BYTE5 FIELD32(0x0000ff00) 101 102/* 103 * CSR5: BSSID register 0. 104 */ 105#define CSR5 0x0014 106#define CSR5_BYTE0 FIELD32(0x000000ff) 107#define CSR5_BYTE1 FIELD32(0x0000ff00) 108#define CSR5_BYTE2 FIELD32(0x00ff0000) 109#define CSR5_BYTE3 FIELD32(0xff000000) 110 111/* 112 * CSR6: BSSID register 1. 113 */ 114#define CSR6 0x0018 115#define CSR6_BYTE4 FIELD32(0x000000ff) 116#define CSR6_BYTE5 FIELD32(0x0000ff00) 117 118/* 119 * CSR7: Interrupt source register. 120 * Write 1 to clear interrupt. 121 * TBCN_EXPIRE: Beacon timer expired interrupt. 122 * TWAKE_EXPIRE: Wakeup timer expired interrupt. 123 * TATIMW_EXPIRE: Timer of atim window expired interrupt. 124 * TXDONE_TXRING: Tx ring transmit done interrupt. 125 * TXDONE_ATIMRING: Atim ring transmit done interrupt. 126 * TXDONE_PRIORING: Priority ring transmit done interrupt. 127 * RXDONE: Receive done interrupt. 128 */ 129#define CSR7 0x001c 130#define CSR7_TBCN_EXPIRE FIELD32(0x00000001) 131#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) 132#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) 133#define CSR7_TXDONE_TXRING FIELD32(0x00000008) 134#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) 135#define CSR7_TXDONE_PRIORING FIELD32(0x00000020) 136#define CSR7_RXDONE FIELD32(0x00000040) 137 138/* 139 * CSR8: Interrupt mask register. 140 * Write 1 to mask interrupt. 141 * TBCN_EXPIRE: Beacon timer expired interrupt. 142 * TWAKE_EXPIRE: Wakeup timer expired interrupt. 143 * TATIMW_EXPIRE: Timer of atim window expired interrupt. 144 * TXDONE_TXRING: Tx ring transmit done interrupt. 145 * TXDONE_ATIMRING: Atim ring transmit done interrupt. 146 * TXDONE_PRIORING: Priority ring transmit done interrupt. 147 * RXDONE: Receive done interrupt. 148 */ 149#define CSR8 0x0020 150#define CSR8_TBCN_EXPIRE FIELD32(0x00000001) 151#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) 152#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) 153#define CSR8_TXDONE_TXRING FIELD32(0x00000008) 154#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) 155#define CSR8_TXDONE_PRIORING FIELD32(0x00000020) 156#define CSR8_RXDONE FIELD32(0x00000040) 157 158/* 159 * CSR9: Maximum frame length register. 160 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. 161 */ 162#define CSR9 0x0024 163#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) 164 165/* 166 * CSR11: Back-off control register. 167 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). 168 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). 169 * SLOT_TIME: Slot time, default is 20us for 802.11b. 170 * LONG_RETRY: Long retry count. 171 * SHORT_RETRY: Short retry count. 172 */ 173#define CSR11 0x002c 174#define CSR11_CWMIN FIELD32(0x0000000f) 175#define CSR11_CWMAX FIELD32(0x000000f0) 176#define CSR11_SLOT_TIME FIELD32(0x00001f00) 177#define CSR11_LONG_RETRY FIELD32(0x00ff0000) 178#define CSR11_SHORT_RETRY FIELD32(0xff000000) 179 180/* 181 * CSR12: Synchronization configuration register 0. 182 * All units in 1/16 TU. 183 * BEACON_INTERVAL: Beacon interval, default is 100 TU. 184 * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU. 185 */ 186#define CSR12 0x0030 187#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) 188#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) 189 190/* 191 * CSR13: Synchronization configuration register 1. 192 * All units in 1/16 TU. 193 * ATIMW_DURATION: Atim window duration. 194 * CFP_PERIOD: Cfp period, default is 0 TU. 195 */ 196#define CSR13 0x0034 197#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) 198#define CSR13_CFP_PERIOD FIELD32(0x00ff0000) 199 200/* 201 * CSR14: Synchronization control register. 202 * TSF_COUNT: Enable tsf auto counting. 203 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. 204 * TBCN: Enable tbcn with reload value. 205 * TCFP: Enable tcfp & cfp / cp switching. 206 * TATIMW: Enable tatimw & atim window switching. 207 * BEACON_GEN: Enable beacon generator. 208 * CFP_COUNT_PRELOAD: Cfp count preload value. 209 * TBCM_PRELOAD: Tbcn preload value in units of 64us. 210 */ 211#define CSR14 0x0038 212#define CSR14_TSF_COUNT FIELD32(0x00000001) 213#define CSR14_TSF_SYNC FIELD32(0x00000006) 214#define CSR14_TBCN FIELD32(0x00000008) 215#define CSR14_TCFP FIELD32(0x00000010) 216#define CSR14_TATIMW FIELD32(0x00000020) 217#define CSR14_BEACON_GEN FIELD32(0x00000040) 218#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) 219#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) 220 221/* 222 * CSR15: Synchronization status register. 223 * CFP: ASIC is in contention-free period. 224 * ATIMW: ASIC is in ATIM window. 225 * BEACON_SENT: Beacon is send. 226 */ 227#define CSR15 0x003c 228#define CSR15_CFP FIELD32(0x00000001) 229#define CSR15_ATIMW FIELD32(0x00000002) 230#define CSR15_BEACON_SENT FIELD32(0x00000004) 231 232/* 233 * CSR16: TSF timer register 0. 234 */ 235#define CSR16 0x0040 236#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) 237 238/* 239 * CSR17: TSF timer register 1. 240 */ 241#define CSR17 0x0044 242#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) 243 244/* 245 * CSR18: IFS timer register 0. 246 * SIFS: Sifs, default is 10 us. 247 * PIFS: Pifs, default is 30 us. 248 */ 249#define CSR18 0x0048 250#define CSR18_SIFS FIELD32(0x0000ffff) 251#define CSR18_PIFS FIELD32(0xffff0000) 252 253/* 254 * CSR19: IFS timer register 1. 255 * DIFS: Difs, default is 50 us. 256 * EIFS: Eifs, default is 364 us. 257 */ 258#define CSR19 0x004c 259#define CSR19_DIFS FIELD32(0x0000ffff) 260#define CSR19_EIFS FIELD32(0xffff0000) 261 262/* 263 * CSR20: Wakeup timer register. 264 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. 265 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. 266 * AUTOWAKE: Enable auto wakeup / sleep mechanism. 267 */ 268#define CSR20 0x0050 269#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) 270#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) 271#define CSR20_AUTOWAKE FIELD32(0x01000000) 272 273/* 274 * CSR21: EEPROM control register. 275 * RELOAD: Write 1 to reload eeprom content. 276 * TYPE_93C46: 1: 93c46, 0:93c66. 277 */ 278#define CSR21 0x0054 279#define CSR21_RELOAD FIELD32(0x00000001) 280#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) 281#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) 282#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) 283#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) 284#define CSR21_TYPE_93C46 FIELD32(0x00000020) 285 286/* 287 * CSR22: CFP control register. 288 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. 289 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. 290 */ 291#define CSR22 0x0058 292#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) 293#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) 294 295/* 296 * Transmit related CSRs. 297 * Some values are set in TU, whereas 1 TU == 1024 us. 298 */ 299 300/* 301 * TXCSR0: TX Control Register. 302 * KICK_TX: Kick tx ring. 303 * KICK_ATIM: Kick atim ring. 304 * KICK_PRIO: Kick priority ring. 305 * ABORT: Abort all transmit related ring operation. 306 */ 307#define TXCSR0 0x0060 308#define TXCSR0_KICK_TX FIELD32(0x00000001) 309#define TXCSR0_KICK_ATIM FIELD32(0x00000002) 310#define TXCSR0_KICK_PRIO FIELD32(0x00000004) 311#define TXCSR0_ABORT FIELD32(0x00000008) 312 313/* 314 * TXCSR1: TX Configuration Register. 315 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. 316 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. 317 * TSF_OFFSET: Insert tsf offset. 318 * AUTORESPONDER: Enable auto responder which include ack & cts. 319 */ 320#define TXCSR1 0x0064 321#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) 322#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) 323#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) 324#define TXCSR1_AUTORESPONDER FIELD32(0x01000000) 325 326/* 327 * TXCSR2: Tx descriptor configuration register. 328 * TXD_SIZE: Tx descriptor size, default is 48. 329 * NUM_TXD: Number of tx entries in ring. 330 * NUM_ATIM: Number of atim entries in ring. 331 * NUM_PRIO: Number of priority entries in ring. 332 */ 333#define TXCSR2 0x0068 334#define TXCSR2_TXD_SIZE FIELD32(0x000000ff) 335#define TXCSR2_NUM_TXD FIELD32(0x0000ff00) 336#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) 337#define TXCSR2_NUM_PRIO FIELD32(0xff000000) 338 339/* 340 * TXCSR3: TX Ring Base address register. 341 */ 342#define TXCSR3 0x006c 343#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) 344 345/* 346 * TXCSR4: TX Atim Ring Base address register. 347 */ 348#define TXCSR4 0x0070 349#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) 350 351/* 352 * TXCSR5: TX Prio Ring Base address register. 353 */ 354#define TXCSR5 0x0074 355#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) 356 357/* 358 * TXCSR6: Beacon Base address register. 359 */ 360#define TXCSR6 0x0078 361#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) 362 363/* 364 * TXCSR7: Auto responder control register. 365 * AR_POWERMANAGEMENT: Auto responder power management bit. 366 */ 367#define TXCSR7 0x007c 368#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) 369 370/* 371 * Receive related CSRs. 372 * Some values are set in TU, whereas 1 TU == 1024 us. 373 */ 374 375/* 376 * RXCSR0: RX Control Register. 377 * DISABLE_RX: Disable rx engine. 378 * DROP_CRC: Drop crc error. 379 * DROP_PHYSICAL: Drop physical error. 380 * DROP_CONTROL: Drop control frame. 381 * DROP_NOT_TO_ME: Drop not to me unicast frame. 382 * DROP_TODS: Drop frame tods bit is true. 383 * DROP_VERSION_ERROR: Drop version error frame. 384 * PASS_CRC: Pass all packets with crc attached. 385 */ 386#define RXCSR0 0x0080 387#define RXCSR0_DISABLE_RX FIELD32(0x00000001) 388#define RXCSR0_DROP_CRC FIELD32(0x00000002) 389#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) 390#define RXCSR0_DROP_CONTROL FIELD32(0x00000008) 391#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) 392#define RXCSR0_DROP_TODS FIELD32(0x00000020) 393#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) 394#define RXCSR0_PASS_CRC FIELD32(0x00000080) 395 396/* 397 * RXCSR1: RX descriptor configuration register. 398 * RXD_SIZE: Rx descriptor size, default is 32b. 399 * NUM_RXD: Number of rx entries in ring. 400 */ 401#define RXCSR1 0x0084 402#define RXCSR1_RXD_SIZE FIELD32(0x000000ff) 403#define RXCSR1_NUM_RXD FIELD32(0x0000ff00) 404 405/* 406 * RXCSR2: RX Ring base address register. 407 */ 408#define RXCSR2 0x0088 409#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) 410 411/* 412 * RXCSR3: BBP ID register for Rx operation. 413 * BBP_ID#: BBP register # id. 414 * BBP_ID#_VALID: BBP register # id is valid or not. 415 */ 416#define RXCSR3 0x0090 417#define RXCSR3_BBP_ID0 FIELD32(0x0000007f) 418#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) 419#define RXCSR3_BBP_ID1 FIELD32(0x00007f00) 420#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) 421#define RXCSR3_BBP_ID2 FIELD32(0x007f0000) 422#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) 423#define RXCSR3_BBP_ID3 FIELD32(0x7f000000) 424#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) 425 426/* 427 * RXCSR4: BBP ID register for Rx operation. 428 * BBP_ID#: BBP register # id. 429 * BBP_ID#_VALID: BBP register # id is valid or not. 430 */ 431#define RXCSR4 0x0094 432#define RXCSR4_BBP_ID4 FIELD32(0x0000007f) 433#define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080) 434#define RXCSR4_BBP_ID5 FIELD32(0x00007f00) 435#define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000) 436 437/* 438 * ARCSR0: Auto Responder PLCP config register 0. 439 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data. 440 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id. 441 */ 442#define ARCSR0 0x0098 443#define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff) 444#define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00) 445#define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000) 446#define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000) 447 448/* 449 * ARCSR1: Auto Responder PLCP config register 1. 450 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data. 451 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id. 452 */ 453#define ARCSR1 0x009c 454#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) 455#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) 456#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) 457#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) 458 459/* 460 * Miscellaneous Registers. 461 * Some values are set in TU, whereas 1 TU == 1024 us. 462 */ 463 464/* 465 * PCICSR: PCI control register. 466 * BIG_ENDIAN: 1: big endian, 0: little endian. 467 * RX_TRESHOLD: Rx threshold in dw to start pci access 468 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. 469 * TX_TRESHOLD: Tx threshold in dw to start pci access 470 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. 471 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. 472 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. 473 */ 474#define PCICSR 0x008c 475#define PCICSR_BIG_ENDIAN FIELD32(0x00000001) 476#define PCICSR_RX_TRESHOLD FIELD32(0x00000006) 477#define PCICSR_TX_TRESHOLD FIELD32(0x00000018) 478#define PCICSR_BURST_LENTH FIELD32(0x00000060) 479#define PCICSR_ENABLE_CLK FIELD32(0x00000080) 480 481/* 482 * CNT0: FCS error count. 483 * FCS_ERROR: FCS error count, cleared when read. 484 */ 485#define CNT0 0x00a0 486#define CNT0_FCS_ERROR FIELD32(0x0000ffff) 487 488/* 489 * Statistic Register. 490 * CNT1: PLCP error count. 491 * CNT2: Long error count. 492 * CNT3: CCA false alarm count. 493 * CNT4: Rx FIFO overflow count. 494 * CNT5: Tx FIFO underrun count. 495 */ 496#define TIMECSR2 0x00a8 497#define CNT1 0x00ac 498#define CNT2 0x00b0 499#define TIMECSR3 0x00b4 500#define CNT3 0x00b8 501#define CNT4 0x00bc 502#define CNT5 0x00c0 503 504/* 505 * Baseband Control Register. 506 */ 507 508/* 509 * PWRCSR0: Power mode configuration register. 510 */ 511#define PWRCSR0 0x00c4 512 513/* 514 * Power state transition time registers. 515 */ 516#define PSCSR0 0x00c8 517#define PSCSR1 0x00cc 518#define PSCSR2 0x00d0 519#define PSCSR3 0x00d4 520 521/* 522 * PWRCSR1: Manual power control / status register. 523 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. 524 * SET_STATE: Set state. Write 1 to trigger, self cleared. 525 * BBP_DESIRE_STATE: BBP desired state. 526 * RF_DESIRE_STATE: RF desired state. 527 * BBP_CURR_STATE: BBP current state. 528 * RF_CURR_STATE: RF current state. 529 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. 530 */ 531#define PWRCSR1 0x00d8 532#define PWRCSR1_SET_STATE FIELD32(0x00000001) 533#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) 534#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) 535#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) 536#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) 537#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) 538 539/* 540 * TIMECSR: Timer control register. 541 * US_COUNT: 1 us timer count in units of clock cycles. 542 * US_64_COUNT: 64 us timer count in units of 1 us timer. 543 * BEACON_EXPECT: Beacon expect window. 544 */ 545#define TIMECSR 0x00dc 546#define TIMECSR_US_COUNT FIELD32(0x000000ff) 547#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) 548#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) 549 550/* 551 * MACCSR0: MAC configuration register 0. 552 */ 553#define MACCSR0 0x00e0 554 555/* 556 * MACCSR1: MAC configuration register 1. 557 * KICK_RX: Kick one-shot rx in one-shot rx mode. 558 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. 559 * BBPRX_RESET_MODE: Ralink bbp rx reset mode. 560 * AUTO_TXBBP: Auto tx logic access bbp control register. 561 * AUTO_RXBBP: Auto rx logic access bbp control register. 562 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. 563 * INTERSIL_IF: Intersil if calibration pin. 564 */ 565#define MACCSR1 0x00e4 566#define MACCSR1_KICK_RX FIELD32(0x00000001) 567#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) 568#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) 569#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) 570#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) 571#define MACCSR1_LOOPBACK FIELD32(0x00000060) 572#define MACCSR1_INTERSIL_IF FIELD32(0x00000080) 573 574/* 575 * RALINKCSR: Ralink Rx auto-reset BBCR. 576 * AR_BBP_DATA#: Auto reset BBP register # data. 577 * AR_BBP_ID#: Auto reset BBP register # id. 578 */ 579#define RALINKCSR 0x00e8 580#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) 581#define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00) 582#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) 583#define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000) 584 585/* 586 * BCNCSR: Beacon interval control register. 587 * CHANGE: Write one to change beacon interval. 588 * DELTATIME: The delta time value. 589 * NUM_BEACON: Number of beacon according to mode. 590 * MODE: Please refer to asic specs. 591 * PLUS: Plus or minus delta time value. 592 */ 593#define BCNCSR 0x00ec 594#define BCNCSR_CHANGE FIELD32(0x00000001) 595#define BCNCSR_DELTATIME FIELD32(0x0000001e) 596#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) 597#define BCNCSR_MODE FIELD32(0x00006000) 598#define BCNCSR_PLUS FIELD32(0x00008000) 599 600/* 601 * BBP / RF / IF Control Register. 602 */ 603 604/* 605 * BBPCSR: BBP serial control register. 606 * VALUE: Register value to program into BBP. 607 * REGNUM: Selected BBP register. 608 * BUSY: 1: asic is busy execute BBP programming. 609 * WRITE_CONTROL: 1: write BBP, 0: read BBP. 610 */ 611#define BBPCSR 0x00f0 612#define BBPCSR_VALUE FIELD32(0x000000ff) 613#define BBPCSR_REGNUM FIELD32(0x00007f00) 614#define BBPCSR_BUSY FIELD32(0x00008000) 615#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) 616 617/* 618 * RFCSR: RF serial control register. 619 * VALUE: Register value + id to program into rf/if. 620 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). 621 * IF_SELECT: Chip to program: 0: rf, 1: if. 622 * PLL_LD: Rf pll_ld status. 623 * BUSY: 1: asic is busy execute rf programming. 624 */ 625#define RFCSR 0x00f4 626#define RFCSR_VALUE FIELD32(0x00ffffff) 627#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) 628#define RFCSR_IF_SELECT FIELD32(0x20000000) 629#define RFCSR_PLL_LD FIELD32(0x40000000) 630#define RFCSR_BUSY FIELD32(0x80000000) 631 632/* 633 * LEDCSR: LED control register. 634 * ON_PERIOD: On period, default 70ms. 635 * OFF_PERIOD: Off period, default 30ms. 636 * LINK: 0: linkoff, 1: linkup. 637 * ACTIVITY: 0: idle, 1: active. 638 */ 639#define LEDCSR 0x00f8 640#define LEDCSR_ON_PERIOD FIELD32(0x000000ff) 641#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) 642#define LEDCSR_LINK FIELD32(0x00010000) 643#define LEDCSR_ACTIVITY FIELD32(0x00020000) 644 645/* 646 * ASIC pointer information. 647 * RXPTR: Current RX ring address. 648 * TXPTR: Current Tx ring address. 649 * PRIPTR: Current Priority ring address. 650 * ATIMPTR: Current ATIM ring address. 651 */ 652#define RXPTR 0x0100 653#define TXPTR 0x0104 654#define PRIPTR 0x0108 655#define ATIMPTR 0x010c 656 657/* 658 * GPIO and others. 659 */ 660 661/* 662 * GPIOCSR: GPIO control register. 663 */ 664#define GPIOCSR 0x0120 665#define GPIOCSR_BIT0 FIELD32(0x00000001) 666#define GPIOCSR_BIT1 FIELD32(0x00000002) 667#define GPIOCSR_BIT2 FIELD32(0x00000004) 668#define GPIOCSR_BIT3 FIELD32(0x00000008) 669#define GPIOCSR_BIT4 FIELD32(0x00000010) 670#define GPIOCSR_BIT5 FIELD32(0x00000020) 671#define GPIOCSR_BIT6 FIELD32(0x00000040) 672#define GPIOCSR_BIT7 FIELD32(0x00000080) 673 674/* 675 * BBPPCSR: BBP Pin control register. 676 */ 677#define BBPPCSR 0x0124 678 679/* 680 * BCNCSR1: Tx BEACON offset time control register. 681 * PRELOAD: Beacon timer offset in units of usec. 682 */ 683#define BCNCSR1 0x0130 684#define BCNCSR1_PRELOAD FIELD32(0x0000ffff) 685 686/* 687 * MACCSR2: TX_PE to RX_PE turn-around time control register 688 * DELAY: RX_PE low width, in units of pci clock cycle. 689 */ 690#define MACCSR2 0x0134 691#define MACCSR2_DELAY FIELD32(0x000000ff) 692 693/* 694 * ARCSR2: 1 Mbps ACK/CTS PLCP. 695 */ 696#define ARCSR2 0x013c 697#define ARCSR2_SIGNAL FIELD32(0x000000ff) 698#define ARCSR2_SERVICE FIELD32(0x0000ff00) 699#define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000) 700#define ARCSR2_LENGTH FIELD32(0xffff0000) 701 702/* 703 * ARCSR3: 2 Mbps ACK/CTS PLCP. 704 */ 705#define ARCSR3 0x0140 706#define ARCSR3_SIGNAL FIELD32(0x000000ff) 707#define ARCSR3_SERVICE FIELD32(0x0000ff00) 708#define ARCSR3_LENGTH FIELD32(0xffff0000) 709 710/* 711 * ARCSR4: 5.5 Mbps ACK/CTS PLCP. 712 */ 713#define ARCSR4 0x0144 714#define ARCSR4_SIGNAL FIELD32(0x000000ff) 715#define ARCSR4_SERVICE FIELD32(0x0000ff00) 716#define ARCSR4_LENGTH FIELD32(0xffff0000) 717 718/* 719 * ARCSR5: 11 Mbps ACK/CTS PLCP. 720 */ 721#define ARCSR5 0x0148 722#define ARCSR5_SIGNAL FIELD32(0x000000ff) 723#define ARCSR5_SERVICE FIELD32(0x0000ff00) 724#define ARCSR5_LENGTH FIELD32(0xffff0000) 725 726/* 727 * BBP registers. 728 * The wordsize of the BBP is 8 bits. 729 */ 730 731/* 732 * R1: TX antenna control 733 */ 734#define BBP_R1_TX_ANTENNA FIELD8(0x03) 735 736/* 737 * R4: RX antenna control 738 */ 739#define BBP_R4_RX_ANTENNA FIELD8(0x06) 740 741/* 742 * RF registers 743 */ 744 745/* 746 * RF 1 747 */ 748#define RF1_TUNER FIELD32(0x00020000) 749 750/* 751 * RF 3 752 */ 753#define RF3_TUNER FIELD32(0x00000100) 754#define RF3_TXPOWER FIELD32(0x00003e00) 755 756/* 757 * EEPROM content. 758 * The wordsize of the EEPROM is 16 bits. 759 */ 760 761/* 762 * HW MAC address. 763 */ 764#define EEPROM_MAC_ADDR_0 0x0002 765#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 766#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 767#define EEPROM_MAC_ADDR1 0x0003 768#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 769#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 770#define EEPROM_MAC_ADDR_2 0x0004 771#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 772#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 773 774/* 775 * EEPROM antenna. 776 * ANTENNA_NUM: Number of antenna's. 777 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 778 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 779 * RF_TYPE: Rf_type of this adapter. 780 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. 781 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning. 782 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. 783 */ 784#define EEPROM_ANTENNA 0x0b 785#define EEPROM_ANTENNA_NUM FIELD16(0x0003) 786#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) 787#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) 788#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040) 789#define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180) 790#define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200) 791#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) 792 793/* 794 * EEPROM BBP. 795 */ 796#define EEPROM_BBP_START 0x0c 797#define EEPROM_BBP_SIZE 7 798#define EEPROM_BBP_VALUE FIELD16(0x00ff) 799#define EEPROM_BBP_REG_ID FIELD16(0xff00) 800 801/* 802 * EEPROM TXPOWER 803 */ 804#define EEPROM_TXPOWER_START 0x13 805#define EEPROM_TXPOWER_SIZE 7 806#define EEPROM_TXPOWER_1 FIELD16(0x00ff) 807#define EEPROM_TXPOWER_2 FIELD16(0xff00) 808 809/* 810 * DMA descriptor defines. 811 */ 812#define TXD_DESC_SIZE (8 * sizeof(__le32)) 813#define RXD_DESC_SIZE (8 * sizeof(__le32)) 814 815/* 816 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. 817 */ 818 819/* 820 * Word0 821 */ 822#define TXD_W0_OWNER_NIC FIELD32(0x00000001) 823#define TXD_W0_VALID FIELD32(0x00000002) 824#define TXD_W0_RESULT FIELD32(0x0000001c) 825#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) 826#define TXD_W0_MORE_FRAG FIELD32(0x00000100) 827#define TXD_W0_ACK FIELD32(0x00000200) 828#define TXD_W0_TIMESTAMP FIELD32(0x00000400) 829#define TXD_W0_RTS FIELD32(0x00000800) 830#define TXD_W0_IFS FIELD32(0x00006000) 831#define TXD_W0_RETRY_MODE FIELD32(0x00008000) 832#define TXD_W0_AGC FIELD32(0x00ff0000) 833#define TXD_W0_R2 FIELD32(0xff000000) 834 835/* 836 * Word1 837 */ 838#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) 839 840/* 841 * Word2 842 */ 843#define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) 844#define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000) 845 846/* 847 * Word3 & 4: PLCP information 848 * The PLCP values should be treated as if they were BBP values. 849 */ 850#define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) 851#define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00) 852#define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000) 853#define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000) 854#define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000) 855#define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000) 856 857#define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff) 858#define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00) 859#define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000) 860#define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000) 861#define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000) 862#define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000) 863 864/* 865 * Word5 866 */ 867#define TXD_W5_BBCR4 FIELD32(0x0000ffff) 868#define TXD_W5_AGC_REG FIELD32(0x007f0000) 869#define TXD_W5_AGC_REG_VALID FIELD32(0x00800000) 870#define TXD_W5_XXX_REG FIELD32(0x7f000000) 871#define TXD_W5_XXX_REG_VALID FIELD32(0x80000000) 872 873/* 874 * Word6 875 */ 876#define TXD_W6_SK_BUFF FIELD32(0xffffffff) 877 878/* 879 * Word7 880 */ 881#define TXD_W7_RESERVED FIELD32(0xffffffff) 882 883/* 884 * RX descriptor format for RX Ring. 885 */ 886 887/* 888 * Word0 889 */ 890#define RXD_W0_OWNER_NIC FIELD32(0x00000001) 891#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) 892#define RXD_W0_MULTICAST FIELD32(0x00000004) 893#define RXD_W0_BROADCAST FIELD32(0x00000008) 894#define RXD_W0_MY_BSS FIELD32(0x00000010) 895#define RXD_W0_CRC_ERROR FIELD32(0x00000020) 896#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) 897#define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000) 898 899/* 900 * Word1 901 */ 902#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) 903 904/* 905 * Word2 906 */ 907#define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) 908#define RXD_W2_BBR0 FIELD32(0x00ff0000) 909#define RXD_W2_SIGNAL FIELD32(0xff000000) 910 911/* 912 * Word3 913 */ 914#define RXD_W3_RSSI FIELD32(0x000000ff) 915#define RXD_W3_BBR3 FIELD32(0x0000ff00) 916#define RXD_W3_BBR4 FIELD32(0x00ff0000) 917#define RXD_W3_BBR5 FIELD32(0xff000000) 918 919/* 920 * Word4 921 */ 922#define RXD_W4_RX_END_TIME FIELD32(0xffffffff) 923 924/* 925 * Word5 & 6 & 7: Reserved 926 */ 927#define RXD_W5_RESERVED FIELD32(0xffffffff) 928#define RXD_W6_RESERVED FIELD32(0xffffffff) 929#define RXD_W7_RESERVED FIELD32(0xffffffff) 930 931/* 932 * Macros for converting txpower from EEPROM to mac80211 value 933 * and from mac80211 value to register value. 934 * NOTE: Logics in rt2400pci for txpower are reversed 935 * compared to the other rt2x00 drivers. A higher txpower 936 * value means that the txpower must be lowered. This is 937 * important when converting the value coming from the 938 * mac80211 stack to the rt2400 acceptable value. 939 */ 940#define MIN_TXPOWER 31 941#define MAX_TXPOWER 62 942#define DEFAULT_TXPOWER 39 943 944#define __CLAMP_TX(__txpower) \ 945 clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER) 946 947#define TXPOWER_FROM_DEV(__txpower) \ 948 ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER) 949 950#define TXPOWER_TO_DEV(__txpower) \ 951 (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER)) 952 953#endif /* RT2400PCI_H */ 954