| /drivers/net/ethernet/dec/tulip/ |
| H A D | media.c | 206 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); local
219 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
220 iowrite32(csr15val, ioaddr + CSR15); /* Data */
233 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
234 iowrite32(csr15val, ioaddr + CSR15); /* Data */
238 netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
261 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); local
264 ioread32(ioaddr + CSR15);
276 iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); local
278 ioread32(ioaddr + CSR15); /* flus
336 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); local
[all...] |
| H A D | 21142.c | 81 iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15);
89 iowrite16(8, ioaddr + CSR15);
130 iowrite32(tp->mtable->csr15dir, ioaddr + CSR15);
131 iowrite32(tp->mtable->csr15val, ioaddr + CSR15);
133 iowrite16(0x0008, ioaddr + CSR15);
|
| H A D | timer.c | 32 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
|
| H A D | xircom_cb.c | 62 #define CSR15 0x78 macro
95 CSR0, CSR6, CSR7, CSR9, CSR10, CSR15
1022 outl(0x0008, card->io_port + CSR15);
1024 outl(0xa8050000, card->io_port + CSR15);
1026 outl(0xa00f0000, card->io_port + CSR15);
|
| H A D | tulip.h | 121 CSR15 = 0x78, enumerator in enum:tulip_offsets
|
| H A D | de2104x.c | 158 CSR15 = 0x78, enumerator in enum:__anon2158
930 dw32(CSR15, de->media[media].csr15);
946 dr32(CSR13), dr32(CSR14), dr32(CSR15));
|
| H A D | tulip_core.c | 424 iowrite32(0x0008, ioaddr + CSR15);
453 iowrite32(0x0001, ioaddr + CSR15);
558 ioread32(ioaddr + CSR15));
|
| H A D | de4x5.h | 632 #define CSR15 0x00000008 macro
|
| H A D | de4x5.c | 4687 lp->cache.csr15 = CSR15;
4764 lp->cache.csr15 = CSR15;
|
| /drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 75 #define CSR15 0x0f00 /* - Mode Register */ macro
236 * Bit definitions for CSR15 (Mode Register)
|
| H A D | pcnet32.c | 210 #define CSR15 15 macro
950 /* set int loopback in CSR15 */
951 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
952 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1009 x = a->read_csr(ioaddr, CSR15);
1010 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
2612 csr15 = lp->a->read_csr(ioaddr, CSR15);
2619 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2623 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
|
| H A D | ariadne.c | 451 lance->RAP = CSR15; /* Mode Register */
658 lance->RAP = CSR15; /* Mode Register */
674 lance->RAP = CSR15; /* Mode Register */
|
| H A D | atarilance.c | 308 #define CSR15 15 /* promiscuous mode */ macro
1095 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
1106 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
|
| H A D | sun3lance.c | 207 #define CSR15 15 /* promiscuous mode */ macro
914 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
925 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
|
| /drivers/net/wireless/rt2x00/ |
| H A D | rt2400pci.h | 222 * CSR15: Synchronization status register.
227 #define CSR15 0x003c macro
|
| H A D | rt2500pci.h | 299 * CSR15: Synchronization status register.
304 #define CSR15 0x003c macro
|
| H A D | rt2400pci.c | 1697 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
|
| H A D | rt2500pci.c | 1989 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
|